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Gabriel M. Silberman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
    SLS - a fast switch level simulator for verification and fault coverage analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:164-170 [Conf]
  2. Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman
    Architectural Improvements for Data-Driven VLSI Processing Arrays. [Citation Graph (0, 0)][DBLP]
    FPCA, 1989, pp:243-259 [Conf]
  3. Israel Koren, Gabriel M. Silberman
    A Direct Mapping of Algorithms onto VLSI Processing Arrays Based on the Data Flow Approach. [Citation Graph (0, 0)][DBLP]
    ICPP, 1983, pp:335-337 [Conf]
  4. Bilha Mendelson, Gabriel M. Silberman
    An Improved Mapping of Data Flow Programs on a VLSI Array of Processors. [Citation Graph (0, 0)][DBLP]
    ICPP, 1987, pp:871-873 [Conf]
  5. Gabriel M. Silberman, Kemal Ebcioglu
    An architectural framework for migration from CISC to higher performance platforms. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:198-215 [Conf]
  6. Leon J. Osterweil, Gabriel M. Silberman, Kenny Wong
    New Software Engineering Faculty Symposium. [Citation Graph (0, 0)][DBLP]
    ICSE, 2001, pp:813-813 [Conf]
  7. Bilha Mendelson, Gabriel M. Silberman
    Mapping Data Flow Programs on a VLSI Array of Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:72-80 [Conf]
  8. Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman
    Efficient Fault Simulation of CMOS Circuits with Accurate Models. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:520-529 [Conf]
  9. Zeev Barzilai, Vijay S. Iyengar, Barry K. Rosen, Gabriel M. Silberman
    Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:722-731 [Conf]
  10. Gabriel M. Silberman, Ilan Y. Spillinger
    The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:332-339 [Conf]
  11. Gabriel M. Silberman, Ilan Y. Spillinger
    G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:764-772 [Conf]
  12. Kemal Ebcioglu, Randy D. Groves, Ki-Chang Kim, Gabriel M. Silberman, Isaac Ziv
    VLIW Compilation Techniques in a Superscalar Environment. [Citation Graph (0, 0)][DBLP]
    PLDI, 1994, pp:36-48 [Conf]
  13. Gabriel M. Silberman
    Stack Processing Techniques in Delayed-Staging Storage Hierarchies. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1983, v:26, n:11, pp:999-1007 [Journal]
  14. Israel Koren, Bilha Mendelson, Irit Peled, Gabriel M. Silberman
    A Data-Driven VLSI Array for Arbitrary Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1988, v:21, n:10, pp:30-43 [Journal]
  15. Raphael Renous, Gabriel M. Silberman, Ilan Y. Spillinger
    Whistle: A Workbench for Test Development of Library-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:4, pp:27-41 [Journal]
  16. Gabriel M. Silberman, Kemal Ebcioglu
    An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1993, v:26, n:6, pp:39-56 [Journal]
  17. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman
    Using a Hardware Simulation Engine for Custom MOS Structured Designs. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1984, v:28, n:5, pp:564-571 [Journal]
  18. Stephen G. Perelgut, Gabriel M. Silberman, Kelly A. Lyons, Karen Bennet
    Overview: The Centre for Advanced Studies. [Citation Graph (0, 0)][DBLP]
    IBM Systems Journal, 1997, v:36, n:4, pp:474-488 [Journal]
  19. Michael A. Bauer, Gene F. Hoffnagle, J. Howard Johnson, Gabriel M. Silberman
    Introduction. [Citation Graph (0, 0)][DBLP]
    Information Systems Frontiers, 2002, v:4, n:4, pp:359-361 [Journal]
  20. Michael A. Bauer, Gene F. Hoffnagle, J. Howard Johnson, Gabriel M. Silberman
    Introduction. [Citation Graph (0, 0)][DBLP]
    Information Systems Frontiers, 2003, v:5, n:2, pp:127-128 [Journal]
  21. Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman
    Architectural Improvement for a Data-Driven VLSI Processing Array. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:19, n:4, pp:308-322 [Journal]
  22. Paul Erdös, Israel Koren, Shlomo Moran, Gabriel M. Silberman, Shmuel Zaks
    Minimum-Diameter Cyclic Arrangements in Mapping Data-Flow Graphs onto VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    Mathematical Systems Theory, 1988, v:21, n:2, pp:85-98 [Journal]
  23. Gabriel M. Silberman
    The Third International Conference on Parallel Computing Technologies (PaCT-95), Saint Petersburg, Russia. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 1996, v:31, n:2, pp:8-9 [Journal]
  24. Dan Gordon, Israel Koren, Gabriel M. Silberman
    Embedding Tree Stuctures in VLlSI Hexagonal Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:1, pp:104-107 [Journal]
  25. Michael Granski, Israel Koren, Gabriel M. Silberman
    The Effect of Operation Scheduling on the Performance of a Data Flow Computer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:9, pp:1019-1029 [Journal]
  26. Gabriel M. Silberman
    Determining Fault Ratios in Multilevel Delayed-Staging Storage Hierarchies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:4, pp:305-310 [Journal]
  27. Gabriel M. Silberman
    Delayed-Staging Hierarchy Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:11, pp:1029-1037 [Journal]
  28. Gabriel M. Silberman, Ilan Y. Spillinger
    Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:1, pp:66-79 [Journal]
  29. Gabriel M. Silberman, Ilan Y. Spillinger
    RIDDLE: A Foundation for Test Generation on a High-Level Design Description. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:1, pp:80-87 [Journal]
  30. Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
    SLS-a fast switch-level simulator [for MOS]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:8, pp:838-849 [Journal]
  31. Gabriel M. Silberman, Ilan Y. Spillinger
    Using functional fault simulation and the difference fault model to estimate implementation fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1335-1343 [Journal]
  32. Ilan Y. Spillinger, Gabriel M. Silberman
    Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:396-404 [Journal]

  33. Agile architecture methodology: long term strategy interleaved with short term tactics. [Citation Graph (, )][DBLP]


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