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Rob A. Rutenbar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bulent Basaran, Rob A. Rutenbar
    An O(n) Algorithm for Transistor Stacking with Performance Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:221-226 [Conf]
  2. L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen
    Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:298-303 [Conf]
  3. Erik C. Carlson, Rob A. Rutenbar
    Mask Verification on the Connection Machine. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:134-140 [Conf]
  4. Erik C. Carlson, Rob A. Rutenbar
    Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:253-259 [Conf]
  5. John M. Cohn, Rob A. Rutenbar, Steve Young, Chris Malachowsky, Luis Aldaz
    Case studies: Chip design on the bleeding edge (panel session abstract). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:648- [Conf]
  6. Claire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen
    Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:496-501 [Conf]
  7. Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
    A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:42-49 [Conf]
  8. Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley
    MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:945-950 [Conf]
  9. Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar
    Massively Parallel Switch-Level Simulation: A Feasibility Study. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:91-97 [Conf]
  10. Saul A. Kravitz, Rob A. Rutenbar
    Multiprocessor-based placement by simulated annealing. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:567-573 [Conf]
  11. Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley
    Remembrance of circuits past: macromodeling by data mining in large analog design spaces. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:437-442 [Conf]
  12. Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar
    A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:698-703 [Conf]
  13. Sudip Nag, Rob A. Rutenbar
    Performance-Driven Simultaneous Place and Route for Row-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:301-307 [Conf]
  14. Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley
    ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:24-30 [Conf]
  15. Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy
    Survival strategies for mixed-signal systems-on-chip (panel session). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:579-580 [Conf]
  16. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums
    A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:1-6 [Conf]
  17. Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
    Panel: (When) Will FPGAs Kill ASICs? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:321-322 [Conf]
  18. Rob A. Rutenbar, Tony Bonaccio, Teresa H. Y. Meng, Ernesto Perea, Robert Pitts, Charles Sodini, Jim Wieser
    Will Moore's Law rule in the land of analog? [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:633- [Conf]
  19. Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow
    Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:85- [Conf]
  20. Rob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Y. Meng, Reza Rofougaran, James Spoto
    Mixed signals on mixed-signal: the right next technology. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:278-279 [Conf]
  21. Dorothy E. Setliff, Rob A. Rutenbar
    ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:543-548 [Conf]
  22. Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar
    Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:167-172 [Conf]
  23. Saurabh K. Tiwary, Rob A. Rutenbar
    Scalable trajectory methods for on-demand analog macromodel extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:403-408 [Conf]
  24. Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar
    Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:31-36 [Conf]
  25. Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar
    Large-scale placement by grid-warping. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:351-356 [Conf]
  26. Zhong Xiu, Rob A. Rutenbar
    Timing-driven placement by grid-warping. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:585-591 [Conf]
  27. Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley
    A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:155-158 [Conf]
  28. Rob A. Rutenbar
    Future directions for DA machine research (panel session). [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:496-497 [Conf]
  29. Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
    Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:279-280 [Conf]
  30. Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar
    Verifying analog oscillator circuits using forward/backward abstraction refinement. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:257-262 [Conf]
  31. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    A boolean satisfiability-based incremental rerouting approach with application to FPGAs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:560-565 [Conf]
  32. Rob A. Rutenbar
    Synthesis for Industrial-Scale Analog Intellectual Property. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2001, pp:3-6 [Conf]
  33. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:167-175 [Conf]
  34. Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen
    A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:60-68 [Conf]
  35. R. Glenn Wood, Rob A. Rutenbar
    FPGA Routing and Routability Estimation via Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:119-125 [Conf]
  36. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:360-369 [Conf]
  37. Bulent Basaran, Rob A. Rutenbar, L. Richard Carley
    Latchup-aware placement and parasitic-bounded routing of custom analog cells. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:415-421 [Conf]
  38. John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley
    Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:394-397 [Conf]
  39. Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
    A hierarchical decomposition methodology for multistage clock circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:266-273 [Conf]
  40. Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen
    Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:275-282 [Conf]
  41. Prakash Gopalakrishnan, Rob A. Rutenbar
    Direct Transistor-Level Layout for Digital Blocks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:577-0 [Conf]
  42. Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar
    Towards formal verification of analog designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:210-217 [Conf]
  43. Rajeev Jayaraman, Rob A. Rutenbar
    A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:344-347 [Conf]
  44. Michael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley
    ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:350-357 [Conf]
  45. James D. Ma, Rob A. Rutenbar
    Interval-valued reduced order statistical interconnect modeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:460-467 [Conf]
  46. Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen
    Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:- [Conf]
  47. James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning
    Interval-valued statistical modeling of oxide chemical-mechanical polishing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:141-148 [Conf]
  48. Sujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley
    System-level routing of mixed-signal ASICs in WREN. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:394-399 [Conf]
  49. Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar
    Synthesis of manufacturable analog circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:586-593 [Conf]
  50. Sudip K. Nag, Rob A. Rutenbar
    Performance-driven simultaneous place and route for island-style FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:332-338 [Conf]
  51. Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni
    Automatic Hierarchical Design: Fantasy or Reality? (Panel). [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:656-0 [Conf]
  52. Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu
    Static statistical timing analysis for latch-based pipeline designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:468-472 [Conf]
  53. Rob A. Rutenbar
    Design automation for analog: the next generation of tool challenges. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:458-460 [Conf]
  54. Saurabh K. Tiwary, Rob A. Rutenbar
    Faster, parametric trajectory-based macromodels via localized linear reductions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:876-883 [Conf]
  55. Rob A. Rutenbar
    Zen and the Art of Analog Design Automation. [Citation Graph (0, 0)][DBLP]
    IFIP Congress, 1989, pp:911- [Conf]
  56. Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar
    Logic Simulation on Massively Parallel Architectures. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:336-343 [Conf]
  57. Pascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley
    Inverse polarity techniques for high-speed/low-power multipliers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:264-266 [Conf]
  58. Rob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone
    Low-power technology mapping for mixed-swing logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:291-294 [Conf]
  59. Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley
    Device-level early floorplanning algorithms for RF circuits. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:57-64 [Conf]
  60. James D. Z. Ma, Rob A. Rutenbar
    Fast interval-valued statistical interconnect modeling and reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:159-166 [Conf]
  61. Rony Kay, Rob A. Rutenbar
    Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:61-68 [Conf]
  62. Rob A. Rutenbar, John M. Cohn
    Layout tools for analog ICs and mixed-signal SoCs: a survey. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:76-83 [Conf]
  63. Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
    A comparative study of two Boolean formulations of FPGA detailed routing constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:222-227 [Conf]
  64. Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov
    Early research experience with OpenAccess gear: an open source development environment for physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:94-100 [Conf]
  65. Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
    sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:182-187 [Conf]
  66. Amith Singhee, Rob A. Rutenbar
    From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:685-692 [Conf]
  67. Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar
    Testability-oriented channel routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:208-213 [Conf]
  68. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    Satisfiability-Based Detailed FPGA Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:574-577 [Conf]
  69. Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar, Oded Maler
    Time Domain Verification of Oscillator Circuit Properties. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:153, n:3, pp:9-22 [Journal]
  70. Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
    A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:6, pp:688-696 [Journal]
  71. Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley
    Device-level early floorplanning algorithms for RF circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:375-388 [Journal]
  72. Erik C. Carlson, Rob A. Rutenbar
    A Scanline Data Structure Processor for VLSI Geometry Checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:780-794 [Journal]
  73. Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
    OASYS: a framework for analog circuit synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1247-1266 [Journal]
  74. Rony Kay, Rob A. Rutenbar
    Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:672-679 [Journal]
  75. Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar
    Massively parallel switch-level simulation: a feasibility study. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:871-894 [Journal]
  76. Saul A. Kravitz, Rob A. Rutenbar
    Placement by Simulated Annealing on a Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:534-549 [Journal]
  77. James D. Ma, Rob A. Rutenbar
    Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:710-724 [Journal]
  78. Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar
    Integer programming based topology selection of cell-level analog circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:401-412 [Journal]
  79. Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar
    Efficient handling of operating range and manufacturing linevariations in analog cell synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:825-839 [Journal]
  80. Sudip Nag, Rob A. Rutenbar
    Performance-driven simultaneous placement and routing for FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:499-518 [Journal]
  81. Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley
    Synthesis of high-performance analog circuits in ASTRX/OBLX. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:273-294 [Journal]
  82. Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
    A new FPGA detailed routing approach via search-based Booleansatisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:674-684 [Journal]
  83. Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums
    Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:6, pp:703-717 [Journal]
  84. Rob A. Rutenbar, Daniel E. Atkins
    Systolic routing hardware: performance evaluation and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:3, pp:397-410 [Journal]
  85. Rob A. Rutenbar, Trevor N. Mudge, Daniel E. Atkins
    A Class of Cellular Architectures to Support Physical Design Automation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:4, pp:264-278 [Journal]
  86. Dorothy E. Setliff, Rob A. Rutenbar
    On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:783-801 [Journal]
  87. Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
    sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:814-820 [Journal]
  88. Dorothy E. Setliff, Rob A. Rutenbar
    Knowledge Representation and Reasoning in a Software Synthesis Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1992, v:18, n:6, pp:523-533 [Journal]
  89. Amith Singhee, Rob A. Rutenbar
    Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:256-261 [Conf]
  90. Amith Singhee, Rob A. Rutenbar
    Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1379-1384 [Conf]
  91. Zhong Xiu, Rob A. Rutenbar
    Mixed-size placement with fixed macrocells using grid-warping. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:103-110 [Conf]
  92. Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
    Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  93. R. Glenn Wood, Rob A. Rutenbar
    FPGA routing and routability estimation via Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:222-231 [Journal]
  94. J. Y. F. Tong, D. Nagle, Rob A. Rutenbar
    Reducing power by optimizing the necessary precision/range of floating-point arithmetic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:273-286 [Journal]

  95. Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains. [Citation Graph (, )][DBLP]


  96. Verifying really complex systems: on earth and beyond. [Citation Graph (, )][DBLP]


  97. Oil fields, hedge funds, and drugs. [Citation Graph (, )][DBLP]


  98. Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference. [Citation Graph (, )][DBLP]


  99. Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. [Citation Graph (, )][DBLP]


  100. A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer. [Citation Graph (, )][DBLP]


  101. Practical, fast Monte Carlo statistical static timing analysis: why and how. [Citation Graph (, )][DBLP]


  102. Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. [Citation Graph (, )][DBLP]


  103. Analog layout synthesis: what's missing? [Citation Graph (, )][DBLP]


  104. Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. [Citation Graph (, )][DBLP]


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