The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Murat R. Becer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Post-route gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:954-957 [Conf]
  2. Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj
    Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:456-464 [Conf]
  3. Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer
    False-Noise Analysis for Domino Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:784-789 [Conf]
  4. Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh
    Pessimism reduction in crosstalk noise aware STA. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:954-961 [Conf]
  5. Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda
    Delay noise pessimism reduction by logic correlations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:160-167 [Conf]
  6. D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, A. Ardelea, A. Patel
    SOI Transistor Model for Fast Transient Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:120128- [Conf]
  7. Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
    Noise propagation and failure criteria for VLSI designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:587-594 [Conf]
  8. Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
    Signal integrity management in an SoC physical design flow. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:39-46 [Conf]
  9. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Post-Route Gate Sizing for Crosstalk Noise Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:171-176 [Conf]
  10. Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj
    A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:158-0 [Conf]
  11. Murat R. Becer, Ibrahim N. Hajj
    An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:51-58 [Conf]
  12. Murat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj
    Pre-route Noise Estimation in Deep Submicron Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:413-418 [Conf]
  13. Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta
    Static Electromigration Analysis for Signal Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:377-0 [Conf]
  14. Arif Selçuk Ögrenci, Murat R. Becer, Günhan Dündar, Sina Balkir
    Incorporating MOS Transistor Mismatches into Training of Analog Neural Networks. [Citation Graph (0, 0)][DBLP]
    NC, 1998, pp:669-675 [Conf]
  15. Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda
    Early probabilistic noise estimation for capacitively coupled interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:77-83 [Conf]
  16. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Postroute gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1670-1677 [Journal]
  17. Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
    Early probabilistic noise estimation for capacitively coupled interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:337-345 [Journal]
  18. Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
    Crosstalk noise control in an SoC physical design flow. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:488-497 [Journal]
  19. Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer
    Top-k Aggressors Sets in Delay Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:174-179 [Conf]

  20. Transistor level gate modeling for accurate and fast timing, noise, and power analysis. [Citation Graph (, )][DBLP]


  21. Victim alignment in crosstalk aware timing analysis. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.302secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002