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Rajendran Panda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Post-route gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:954-957 [Conf]
  2. David Blaauw, Rajendran Panda, Abhijit Das
    Removing user specified false paths from timing graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:270-273 [Conf]
  3. Rajat Chaudhry, David Blaauw, Rajendran Panda, Tim Edwards
    Current signature compression for IR-drop analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:162-167 [Conf]
  4. Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden
    Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:738-743 [Conf]
  5. Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw
    On-chip inductance modeling and analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:63-68 [Conf]
  6. Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda
    Stochastic variational analysis of large power grids considering intra-die correlations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:211-216 [Conf]
  7. Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw
    Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:388-391 [Conf]
  8. Rajendran Panda, Farid N. Najm
    Technology-Dependent Transformations for Low-Power Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:650-655 [Conf]
  9. Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    A stochastic approach To power grid analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:171-176 [Conf]
  10. Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw
    Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:436-441 [Conf]
  11. Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    Optimal placement of power supply pads and pins. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:165-170 [Conf]
  12. Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw
    Hierarchical analysis of power distribution networks. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:150-155 [Conf]
  13. Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
    A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:217-222 [Conf]
  14. Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj
    Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:456-464 [Conf]
  15. Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang
    Stochastic Power Grid Analysis Considering Process Variations. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:964-969 [Conf]
  16. Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer
    False-Noise Analysis for Domino Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:784-789 [Conf]
  17. Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija
    CMOS Combinational Circuit Sizing by Stage-wise Tapering. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:985-988 [Conf]
  18. David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang
    On-chip inductance modeling. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:75-80 [Conf]
  19. David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
    Slope Propagation in Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:338-343 [Conf]
  20. Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh
    Pessimism reduction in crosstalk noise aware STA. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:954-961 [Conf]
  21. Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, G. Vijayan, David Blaauw
    Library-less synthesis for static CMOS combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:658-662 [Conf]
  22. Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda
    Delay noise pessimism reduction by logic correlations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:160-167 [Conf]
  23. Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
    A precorrected-FFT method for simulating on-chip inductance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:221-227 [Conf]
  24. D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, A. Ardelea, A. Patel
    SOI Transistor Model for Fast Transient Simulation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:120128- [Conf]
  25. Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    Vectorless Analysis of Supply Noise Induced Delay Variation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:184-192 [Conf]
  26. Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
    Noise propagation and failure criteria for VLSI designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:587-594 [Conf]
  27. Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
    Table look-up based compact modeling for on-chip interconnect timing and noise analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:668-671 [Conf]
  28. David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
    Emerging power management tools for processor design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:143-148 [Conf]
  29. Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
    Model and analysis for combined package and on-chip power grid simulation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:179-184 [Conf]
  30. Rajendran Panda, Savithri Sundareswaran, David Blaauw
    On the interaction of power distribution network with substrate. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:388-393 [Conf]
  31. Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
    Signal integrity management in an SoC physical design flow. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:39-46 [Conf]
  32. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Post-Route Gate Sizing for Crosstalk Noise Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:171-176 [Conf]
  33. David Blaauw, Rajendran Panda
    On-Chip Inductance Extraction and Modelin. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:14- [Conf]
  34. Murat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj
    Pre-route Noise Estimation in Deep Submicron Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:413-418 [Conf]
  35. Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh
    False-Noise Analysis Using Resolution Method. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:437-0 [Conf]
  36. Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta
    Static Electromigration Analysis for Signal Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:377-0 [Conf]
  37. Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sun Ku, Rajendran Panda
    A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:232-237 [Conf]
  38. Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh
    Noise Injection and Propagation in High Performance Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:425-430 [Conf]
  39. Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda
    Early probabilistic noise estimation for capacitively coupled interconnects. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:77-83 [Conf]
  40. Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal
    Worst case clock skew under power supply variations. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:22-28 [Conf]
  41. Rajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw
    Design and Analysis of Power Distribution Networks with Accurate RLC Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:151-155 [Conf]
  42. Rajendran Panda, Savithri Sundareswaran, David Blaauw
    Impact of Low-Impedance Substrate on Power Supply Integrity. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:16-22 [Journal]
  43. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Postroute gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1670-1677 [Journal]
  44. Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
    Early probabilistic noise estimation for capacitively coupled interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:337-345 [Journal]
  45. Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
    Crosstalk noise control in an SoC physical design flow. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:488-497 [Journal]
  46. Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda
    Impact of stress-induced backflow on full-chip electromigration risk assessment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1038-1046 [Journal]
  47. Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
    Fast on-chip inductance simulation using a precorrected-FFT method. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:49-66 [Journal]
  48. Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    Optimal placement of power-supply pads and pins. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:144-154 [Journal]
  49. Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw
    Hierarchical analysis of power distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:159-168 [Journal]
  50. Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
    On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:162-167 [Conf]
  51. Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Wang
    Stochastic Power Grid Analysis Considering Process Variations [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  52. Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw
    Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:79-90 [Journal]

  53. A novel technique for incremental analysis of on-chip power distribution networks. [Citation Graph (, )][DBLP]


  54. Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. [Citation Graph (, )][DBLP]


  55. Characterization of Standard Cells for Intra-Cell Mismatch Variations. [Citation Graph (, )][DBLP]


  56. Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. [Citation Graph (, )][DBLP]


  57. Characterization of sequential cells for constraint sensitivities. [Citation Graph (, )][DBLP]


  58. A timing methodology considering within-die clock skew variations. [Citation Graph (, )][DBLP]


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