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Chanhee Oh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Post-route gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:954-957 [Conf]
  2. Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov
    ClariNet: a noise analysis tool for deep submicron design. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:233-238 [Conf]
  3. Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo
    Driver Modeling and Alignment for Worst-Case Delay Noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:720-725 [Conf]
  4. Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw
    Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:436-441 [Conf]
  5. Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer
    False-Noise Analysis for Domino Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:784-789 [Conf]
  6. Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer
    Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:332-337 [Conf]
  7. David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
    Slope Propagation in Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:338-343 [Conf]
  8. Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh
    Pessimism reduction in crosstalk noise aware STA. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:954-961 [Conf]
  9. Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov
    False-Noise Analysis using Logic Implications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:515-0 [Conf]
  10. Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda
    Delay noise pessimism reduction by logic correlations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:160-167 [Conf]
  11. Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
    Noise propagation and failure criteria for VLSI designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:587-594 [Conf]
  12. David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
    Emerging power management tools for processor design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:143-148 [Conf]
  13. Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
    Signal integrity management in an SoC physical design flow. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:39-46 [Conf]
  14. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Post-Route Gate Sizing for Crosstalk Noise Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:171-176 [Conf]
  15. Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj
    A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:158-0 [Conf]
  16. Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh
    False-Noise Analysis Using Resolution Method. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:437-0 [Conf]
  17. Mini Nanua, David Blaauw, Chanhee Oh
    Leakage Current Modeling in PD SOI Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:113-117 [Conf]
  18. Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta
    Static Electromigration Analysis for Signal Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:377-0 [Conf]
  19. Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sun Ku, Rajendran Panda
    A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:232-237 [Conf]
  20. Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh
    Noise Injection and Propagation in High Performance Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:425-430 [Conf]
  21. David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta
    Static electromigration analysis for on-chip signal interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:39-48 [Journal]
  22. Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
    Postroute gate sizing for crosstalk noise reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1670-1677 [Journal]
  23. Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
    Crosstalk noise control in an SoC physical design flow. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:488-497 [Journal]
  24. Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda
    Impact of stress-induced backflow on full-chip electromigration risk assessment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1038-1046 [Journal]
  25. Chanhee Oh, M. Ray Mercer
    Efficient logic-level timing analysis using constraint-guided critical path search. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:3, pp:346-355 [Journal]
  26. Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw
    Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:79-90 [Journal]
  27. David Blaauw, Supamas Sirichotiyakul, Chanhee Oh
    Driver modeling and alignment for worst-case delay noise. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:157-166 [Journal]

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