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Alberto Macii:
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Publications of Author
- Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP] DAC, 2001, pp:784-789 [Conf]
- Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino
Energy-aware design techniques for differential power analysis protection. [Citation Graph (0, 0)][DBLP] DAC, 2003, pp:36-41 [Conf]
- Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Synthesis of application-specific memories for power optimization in embedded systems. [Citation Graph (0, 0)][DBLP] DAC, 2000, pp:300-303 [Conf]
- Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses. [Citation Graph (0, 0)][DBLP] DAC, 1999, pp:128-133 [Conf]
- Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. [Citation Graph (0, 0)][DBLP] DATE, 2002, pp:449-450 [Conf]
- Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
A Discrete-Time Battery Model for High-Level Power Estimation. [Citation Graph (0, 0)][DBLP] DATE, 2000, pp:35-0 [Conf]
- Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
Enabling fine-grain leakage management by voltage anchor insertion. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:868-873 [Conf]
- Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Extending lifetime of portable systems by battery scheduling. [Citation Graph (0, 0)][DBLP] DATE, 2001, pp:197-203 [Conf]
- Luca Benini, Alessandro Ivaldi, Alberto Macii, Enrico Macii
Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:698-699 [Conf]
- Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Glitch Power Minimization by Gate Freezing. [Citation Graph (0, 0)][DBLP] DATE, 1999, pp:163-167 [Conf]
- Ashutosh Chakraborty, Prassanna Sithambaram, K. Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino
Thermal resilient bounded-skew clock tree optimization methodology. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:832-837 [Conf]
- Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP] DATE, 2003, pp:10024-10029 [Conf]
- Alberto Macii, Enrico Macii, Massimo Poncino
Improving the Efficiency of Memory Partitioning by Address Clustering. [Citation Graph (0, 0)][DBLP] DATE, 2003, pp:10018-10023 [Conf]
- Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems. [Citation Graph (0, 0)][DBLP] EUROMICRO, 1999, pp:1311-1317 [Conf]
- Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. [Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1998, pp:8-12 [Conf]
- Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro
A novel architecture for power maskable arithmetic units. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2003, pp:136-140 [Conf]
- Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
Low-overhead state-retaining elements for low-leakage MTCMOS design. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:367-370 [Conf]
- Luca Benini, Marco Ferrero, Alberto Macii, Enrico Macii, Massimo Poncino
Supporting system-level power exploration for DSP applications. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:17-22 [Conf]
- Monica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
Enhanced clustered voltage scaling for low power. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2002, pp:18-23 [Conf]
- Alberto Macii, Enrico Macii, Giuseppe Odasso, Massimo Poncino, Riccardo Scarsi
Regression-Based Macromodeling for Delay Estimation of Behavioral Components. [Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1999, pp:188-191 [Conf]
- Prassanna Sithambaram, Alberto Macii, Enrico Macii
Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:377-380 [Conf]
- Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2007, pp:501-504 [Conf]
- Fabrizio Ferrandi, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi, Fabio Somenzi
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits. [Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:235-241 [Conf]
- Alberto Macii, Enrico Macii, Massimo Poncino
Increasing the locality of memory access patterns by low-overhead hardware address relocation. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:385-388 [Conf]
- Luca Benini, Davide Bruni, Bruno Riccò, Alberto Macii, Enrico Macii
An adaptive data compression scheme for memory traffic minimization in processor-based systems. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2002, pp:866-869 [Conf]
- Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino
Energy-efficient data scrambling on memory-processor interfaces. [Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:26-29 [Conf]
- Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Discharge current steering for battery lifetime optimization. [Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:118-123 [Conf]
- Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Selective instruction compression for memory energy reduction in embedded systems. [Citation Graph (0, 0)][DBLP] ISLPED, 1999, pp:206-211 [Conf]
- Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
Post-layout leakage power minimization based on distributed sleep transistor insertion. [Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:138-143 [Conf]
- Luca Benini, Alberto Macii, Alberto Nannarelli
Cached-code compression for energy minimization in embedded processors. [Citation Graph (0, 0)][DBLP] ISLPED, 2001, pp:322-327 [Conf]
- Luca Benini, Alberto Macii, Massimo Poncino
A recursive algorithm for low-power memory partitioning. [Citation Graph (0, 0)][DBLP] ISLPED, 2000, pp:78-83 [Conf]
- Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Stream synthesis for efficient power simulation based on spectral transforms. [Citation Graph (0, 0)][DBLP] ISLPED, 1998, pp:30-35 [Conf]
- Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic thermal clock skew compensation using tunable delay buffers. [Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:162-167 [Conf]
- Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Riccardo Scarsi
Battery-Driven Dynamic Power Management of Portable Systems. [Citation Graph (0, 0)][DBLP] ISSS, 2000, pp:25-33 [Conf]
- Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization. [Citation Graph (0, 0)][DBLP] ISVLSI, 2003, pp:250-251 [Conf]
- Luca Benini, Alberto Macii, Enrico Macii
Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems. [Citation Graph (0, 0)][DBLP] PATMOS, 2002, pp:314-322 [Conf]
- Maurizio Bruno, Alberto Macii, Massimo Poncino
A Statistic Power Model for Non-synthetic RTL Operators. [Citation Graph (0, 0)][DBLP] PATMOS, 2003, pp:208-218 [Conf]
- Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. [Citation Graph (0, 0)][DBLP] PATMOS, 2006, pp:214-224 [Conf]
- Prassanna Sithambaram, Alberto Macii, Enrico Macii
Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs. [Citation Graph (0, 0)][DBLP] PATMOS, 2005, pp:477-487 [Conf]
- Luca Benini, Giuliano Castelli, Alberto Macii, Riccardo Scarsi
Battery-Driven Dynamic Power Management. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2001, v:18, n:2, pp:53-60 [Journal]
- Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2000, v:17, n:2, pp:74-85 [Journal]
- Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii, Massimo Poncino
Discharge Current Steering for Battery Lifetime Optimization. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2003, v:52, n:8, pp:985-995 [Journal]
- Luca Benini, Alberto Macii, Massimo Poncino, Riccardo Scarsi
Architectures and synthesis algorithms for power-efficient businterfaces. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:969-980 [Journal]
- Luca Benini, Alberto Macii, Massimo Poncino
Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques. [Citation Graph (0, 0)][DBLP] ACM Trans. Embedded Comput. Syst., 2003, v:2, n:1, pp:5-32 [Journal]
- Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
Memory energy minimization by data compression: algorithms, architectures and implementation. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:255-268 [Journal]
- A. Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1544-1549 [Conf]
- K. Duraisami, Prassanna Sithambaram, A. Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. [Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:1061-1064 [Conf]
- Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. [Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf]
- Prassanna Sithambaram, Alberto Macii, Enrico Macii
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses. [Citation Graph (0, 0)][DBLP] PATMOS, 2007, pp:232-241 [Conf]
- Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Glitch power minimization by selective gate freezing. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:287-298 [Journal]
- Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Discrete-time battery models for system-level low-power design. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:630-640 [Journal]
- Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Stream synthesis for efficient power simulation based on spectral transforms. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2001, v:9, n:3, pp:417-426 [Journal]
- Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
Minimizing memory access energy in embedded systems by selective instruction compression. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:521-531 [Journal]
- Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino
Layout-driven memory synthesis for embedded systems-on-chip. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:96-105 [Journal]
- Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Scheduling battery usage in mobile systems. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1136-1143 [Journal]
A Scalable Algorithmic Framework for Row-Based Power-Gating. [Citation Graph (, )][DBLP]
Enabling concurrent clock and power gating in an industrial design flow. [Citation Graph (, )][DBLP]
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. [Citation Graph (, )][DBLP]
Optimal sleep transistor synthesis under timing and area constraints. [Citation Graph (, )][DBLP]
An integrated thermal estimation framework for industrial embedded platforms. [Citation Graph (, )][DBLP]
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. [Citation Graph (, )][DBLP]
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. [Citation Graph (, )][DBLP]
Timing-driven row-based power gating. [Citation Graph (, )][DBLP]
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. [Citation Graph (, )][DBLP]
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. [Citation Graph (, )][DBLP]
Data-Driven Clock Gating for Digital Filters. [Citation Graph (, )][DBLP]
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