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Jacques Benkoski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jacques Benkoski, Andrzej J. Strojwas
    Timing Verification by Formal Signal Interaction Modeling in a Multi-level Timing Simulator. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:668-673 [Conf]
  2. Jacques Benkoski, Andrzej J. Strojwas
    The Role of Timing Verification in Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:612-619 [Conf]
  3. K. Brock, C. Edwards, R. Lannoo, Ulf Schlichtmann, Antun Domic, Jacques Benkoski, David Overhauser, M. Kliment
    Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:538-539 [Conf]
  4. Ronald Stewart, Jacques Benkoski
    Static Timing Analysis Using Interval Constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:308-311 [Conf]
  5. Bill Alexander, Jacques Benkoski
    0.13 micron: Will the Speed Bumps Slow the Race to Market? [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:229-0 [Conf]
  6. Robert N. Blair, Jacques Benkoski
    How Do You Select A High Quality EDA Tool Flow?. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:17-0 [Conf]
  7. Jacques Benkoski, Michelle Clancy, Shankar Krishnamoorthy, David Holt, Ravi Subramanian, Clive Bittlestone, Tsuyoshi Yamamoto, Andrew Kanhg
    Do Digital Design and Variability Mix like Oil and Water? [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:672-676 [Conf]
  8. Jacques Benkoski, Andrzej J. Strojwas
    Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:153-160 [Conf]
  9. Jacques Benkoski, E. Vanden Meersch, Luc J. M. Claesen, Hugo De Man
    Timing verification using statically sensitizable paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:10, pp:10723-10784 [Journal]
  10. Jacques Benkoski, Andrzej J. Strojwas
    A New Approach to Hierarchical and Statistical Timing Simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:6, pp:1039-1052 [Journal]

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