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Debashis Bhattacharya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal
    Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:159-164 [Conf]
  2. Ted Stanion, Debashis Bhattacharya
    TSUNAMI: A Path Oriented Scheme for Algebraic Test Generation. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:36-43 [Conf]
  3. Debashis Bhattacharya, Prathima Agrawal
    Boolean algebraic test generation using a distributed system. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:440-443 [Conf]
  4. Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya
    Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:120-125 [Conf]
  5. Shang-E Tai, Debashis Bhattacharya
    Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:564-567 [Conf]
  6. Debashis Bhattacharya
    Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak Buffer. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:174-180 [Conf]
  7. Debashis Bhattacharya, S. Freeman, W. Lin
    Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:289-296 [Conf]
  8. Kumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal
    Architecture of a Min-Max Simulator on MARS. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:246-249 [Conf]
  9. Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya
    Algorithms for Low Power FIR Filter Realization Using Differential Coefficients. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:174-178 [Conf]
  10. Shang-E Tai, Debashis Bhattacharya
    A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:101-106 [Conf]
  11. Debashis Bhattacharya
    Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:8-14 [Conf]
  12. Debashis Bhattacharya
    Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:467-472 [Conf]
  13. Debashis Bhattacharya, Brian T. Murray, John P. Hayes
    High-Level Test Generation for VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:4, pp:16-24 [Journal]
  14. Rob Roy, Debashis Bhattacharya, Vamsi Boppana
    Transistor-Level Optimization of Digital Designs with Flex Cells. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2005, v:38, n:2, pp:53-61 [Journal]
  15. Debashis Bhattacharya, Satyabroto Sinha
    Invariance of stereo images via the theory of complex moments. [Citation Graph (0, 0)][DBLP]
    Pattern Recognition, 1997, v:30, n:9, pp:1373-1386 [Journal]
  16. Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal
    Test Generation for Path Delay Faults Using Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:434-447 [Journal]
  17. Debashis Bhattacharya, John P. Hayes
    Designing for high-level test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:752-766 [Journal]
  18. Ted Stanion, Debashis Bhattacharya, Carl Sechen
    An efficient method for generating exhaustive test sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1516-1525 [Journal]

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