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Publications of Author

1. Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy
   A novel synthesis approach for active leakage power reduction using dynamic supply gating. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:479-484 [Conf]
   
2. Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy
   Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:983-988 [Conf]
   
3. Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy
   Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. [Citation Graph (0, 0)][DBLP]
   DDECS, 2007, pp:69-74 [Conf]
   
4. Matthew Cooke, Hamid Mahmoodi-Meimand, Qikai Chen, Kaushik Roy
   Energy recovery clocked dynamic logic. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:468-471 [Conf]
   
5. Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy
   A Soft Error Monitor Using Switching Current Detection. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:185-192 [Conf]
   
6. Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy
   Process Variation Tolerant Online Current Monitor for Robust Systems. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2005, pp:171-176 [Conf]
   
7. Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy
   Analysis of super cut-off transistors for ultralow power digital logic circuits. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2006, pp:2-7 [Conf]
   
8. Qikai Chen, Mesut Meterelliyoz, Kaushik Roy
   A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design. [Citation Graph (0, 0)][DBLP]
   ISQED, 2006, pp:243-248 [Conf]
   
9. Qikai Chen, Arjun Guha, Kaushik Roy
   An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2007, pp:615-620 [Conf]
   
10. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
    Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:292-297 [Conf]
    
11. Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy
    Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1286-1295 [Journal]