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Jaume Segura: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Swarup Bhunia, Kaushik Roy, Jaume Segura
    A novel wavelet transform based transient current analysis for fault detection and localization. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:361-366 [Conf]
  2. Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
    Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:464-465 [Conf]
  3. José Luis Rosselló, V. Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
    A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:206-211 [Conf]
  4. José Luis Rosselló, Jaume Segura
    A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:954-961 [Conf]
  5. José Luis Rosselló, Jaume Segura
    A compact model to identify delay faults due to crosstalk. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:902-906 [Conf]
  6. Jaume Segura
    CMOS Testing at the End of the Roadmap: Challenges and Opportunities. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:2- [Conf]
  7. Charles F. Hawkins, Ali Keshavarzi, Jaume Segura
    A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:267-0 [Conf]
  8. José Luis Rosselló, Jaume Segura
    Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:494-0 [Conf]
  9. B. Alorda, V. Canals, I. de Paúl, Jaume Segura
    A BIST-based Charge Analysis for Embedded Memories. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:199-206 [Conf]
  10. B. Alorda, André Ivanov, Jaume Segura
    An Off-Chip Sensor Circuit for On-Line Transient Current Testing. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:192- [Conf]
  11. B. Alorda, I. de Paúl, Jaume Segura, T. Miller
    On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2000, pp:87-91 [Conf]
  12. B. Alorda, Jaume Segura
    An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2003, pp:178-182 [Conf]
  13. Joan Font, J. Ginard, Eugeni Isern, Miquel Roca, Jaume Segura, Eugenio García
    A BICS for CMOS Opamps by Monitoring the Supply Current Peak. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:94-98 [Conf]
  14. B. Alorda, Sebastià A. Bota, Jaume Segura
    A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:177-182 [Conf]
  15. B. Alorda, B. Bloechel, Ali Keshavarzi, Jaume Segura
    CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:719-726 [Conf]
  16. B. Alorda, M. Rosales, Jerry M. Soden, Charles F. Hawkins, Jaume Segura
    Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:947-953 [Conf]
  17. Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi
    Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1276-1284 [Conf]
  18. Jaume Segura, Carol de Benito, A. Rubio, Charles F. Hawkins
    A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:544-551 [Conf]
  19. Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins
    Parametric Failures in CMOS ICs - A Defect-Based Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:90-99 [Conf]
  20. José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
    Leakage Power Characterization Considering Process Variations. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:66-74 [Conf]
  21. José Luis Rosselló, Sebastià A. Bota, Jaume Segura
    Compact Static Power Model of Complex CMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:348-354 [Conf]
  22. José Luis Rosselló, Jaume Segura
    A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:219-228 [Conf]
  23. José Luis Rosselló, Jaume Segura
    A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:51-59 [Conf]
  24. Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
    Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:358-363 [Conf]
  25. E. Isern, M. Roca, J. Segura
    Analyzing the Need for ATPG Targeting GOS Defects. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:420-425 [Conf]
  26. I. de Paúl, M. Rosales, B. Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden
    Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:286-291 [Conf]
  27. Jaume Segura, Vivek De, Ali Keshavarzi
    Challenges in Nanometric Technology Scaling: Trends and Projections. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:447-448 [Conf]
  28. Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura
    Impact of Thermal Gradients on Clock Skew and Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:414-424 [Journal]
  29. Charles F. Hawkins, Jaume Segura
    Test and Reliability: Partners in IC Manufacturing, Part 1. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:3, pp:64-71 [Journal]
  30. Charles F. Hawkins, Jaume Segura, Jerry M. Soden, Ted Dellin
    Test and Reliability: Partners in IC Manufacturing, Part 2. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:4, pp:66-73 [Journal]
  31. Jaume Segura, Peter C. Maxwell
    Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:5-7 [Journal]
  32. José Luis Rosselló, Jaume Segura
    Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:433-448 [Journal]
  33. José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
    Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1271-1276 [Conf]
  34. X. Cano, Sebastià A. Bota, R. Graciani, D. Gascón, A. Herms, A. Comerma, Jaume Segura, L. Garrido
    Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:183-184 [Conf]
  35. Sebstatià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
    Smart Temperature Sensor for Thermal Testing of Cell-Based ICs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  36. José Luis Rosselló, V. Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
    A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  37. Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. [Citation Graph (, )][DBLP]


  38. A Fully CMOS Low-Cost Chaotic Neural Network. [Citation Graph (, )][DBLP]


  39. Using stochastic logic for efficient pattern recognition analysis. [Citation Graph (, )][DBLP]


  40. Automated agent-based system for weather information. [Citation Graph (, )][DBLP]


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