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Chi-Yuan Lo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Charles R. Bonapace, Chi-Yuan Lo
    An O(nlogm) Algorithm for VLSI Design Rule Checking. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:503-507 [Conf]
  2. Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
    Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:471-475 [Conf]
  3. Debaprosad Dutt, Chi-Yuan Lo
    On Minimal Closure Constraint Generation for Symbolic Cell Assembly. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:736-739 [Conf]
  4. Chi-Yuan Lo
    Automatic Tub Region Generation for Symbolic Layout Compaction. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:302-306 [Conf]
  5. Chi-Yuan Lo, Ravi Varadarajan
    An O(n1.5logn) 1-d Compaction Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:382-387 [Conf]
  6. Chong-Leong Ong, Jeong-Tyng Li, Chi-Yuan Lo
    GENAC: An Automatic Cell Synthesis Tool. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:239-244 [Conf]
  7. H. Shin, Chi-Yuan Lo
    An Efficient Two-Dimensional Layout Compaction Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:290-295 [Conf]
  8. So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
    Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:395-400 [Conf]
  9. Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu
    HS: A Hierarchical Search Package for CAD Data. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:478-481 [Conf]
  10. Anoop Singhal, Robert M. Arlein, Chi-Yuan Lo
    DDB: An Object Oriented Design Data Manager for VLSI CAD. [Citation Graph (0, 0)][DBLP]
    SIGMOD Conference, 1993, pp:467-470 [Conf]
  11. Chi-Yuan Lo, Jirí Matousek, William L. Steiger
    Ham-Sandwich Cuts in R^d [Citation Graph (0, 0)][DBLP]
    STOC, 1992, pp:539-545 [Conf]
  12. Anoop Singhal, Chi-Yuan Lo
    Object oriented data modeling for VLSI/CAD. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:25-29 [Conf]
  13. Chi-Yuan Lo, Jirí Matousek, William L. Steiger
    Algorithms for Ham-Sandwich Cuts. [Citation Graph (0, 0)][DBLP]
    Discrete & Computational Geometry, 1994, v:11, n:, pp:433-452 [Journal]
  14. Charles R. Bonapace, Chi-Yuan Lo
    An O(n log m) algorithm for VLSI design rule checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:6, pp:753-758 [Journal]
  15. Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
    Time-efficient VLSI artwork analysis algorithms in GOALIE2. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:640-648 [Journal]
  16. Chi-Yuan Lo, Hao N. Nham, Ajoy K. Bose
    Algorithms for an Advanced Fault Simulation System in MOTIS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:2, pp:232-240 [Journal]
  17. Nishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu
    HS: a hierarchical search package for CAD data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:1-5 [Journal]
  18. Shun-Lin Su, Charles H. Barry, Chi-Yuan Lo
    A space-efficient short-finding algorithm [VLSI layouts]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:8, pp:1065-1068 [Journal]
  19. So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
    A cell-based hierarchical pitchmatching compaction using minimal LP. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:523-526 [Journal]

  20. A Wireless Human Motion Capturing System for Home Rehabilitation. [Citation Graph (, )][DBLP]


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