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Shekhar Y. Borkar :
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Shekhar Y. Borkar , Robert W. Brodersen , Jue-Hsien Chern , Eric Naviasky , D. Saias , Charles Sodini Tomorrow's analog: just dead or just different? [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:709-710 [Conf ] Richard Goldman , Kurt Keutzer , Clive Bittlestone , Ahsan Bootehsaz , Shekhar Y. Borkar , E. Chen , Louis Scheffer , Chandramouli Visweswariah Is statistical timing statistically significant? [Citation Graph (0, 0)][DBLP ] DAC, 2004, pp:498- [Conf ] Steven Hsu , Amit Agarwal , Kaushik Roy , Ram Krishnamurthy , Shekhar Y. Borkar An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. [Citation Graph (0, 0)][DBLP ] ISLPED, 2005, pp:103-106 [Conf ] Shekhar Y. Borkar Microarchitecture and Design Challenges for Gigascale Integration. [Citation Graph (0, 0)][DBLP ] MICRO, 2004, pp:3- [Conf ] Shekhar Y. Borkar VLSI Design Challenges for Gigascale Integration. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2005, pp:27-0 [Conf ] Shekhar Y. Borkar Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2005, v:25, n:6, pp:10-16 [Journal ] Circuit techniques for dynamic variation tolerance. [Citation Graph (, )][DBLP ] Want to be a bug buster? [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.002secs