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Tanay Karnik: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shekhar Borkar, Tanay Karnik, Vivek De
    Design and reliability challenges in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:75- [Conf]
  2. Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De
    Parameter variations and impact on circuits and microarchitecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:338-342 [Conf]
  3. Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
    Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:486-491 [Conf]
  4. Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang
    Logic soft errors in sub-65nm technologies design and CAD challenges. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:2-4 [Conf]
  5. Tsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik
    HiSIM: hierarchical interconnect-centric circuit simulator. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:489-496 [Conf]
  6. Tanay Karnik, Shekhar Borkar, Vivek De
    Sub-90nm technologies: challenges and opportunities for CAD. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:203-206 [Conf]
  7. Tanay Karnik, Sung-Mo Kang
    An empirical model for accurate estimation of routing delay in FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:328-331 [Conf]
  8. Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald Gardner, Siva Narendra, Tanay Karnik, Vivek De
    Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:263-268 [Conf]
  9. Changbo Long, Sasank Reddy, Sudhakar Pamarti, Lei He, Tanay Karnik
    Power-efficient pulse width modulation DC/DC converters with zero voltage switching control. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:326-329 [Conf]
  10. Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
    Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:156-161 [Conf]
  11. Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi
    Design of sub-90nm Circuits and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:3-4 [Conf]
  12. Peter Hazucha, Fabrice Paillet, Sung Tae Moon, David J. Rennie, Gerhard Schrom, Donald S. Gardner, Kenneth Ikeda, Gell Gellman, Tanay Karnik
    Low Voltage Buffered Bandgap Reference. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:93-97 [Conf]
  13. Ruchir Puri, Tanay Karnik, Rajiv V. Joshi
    Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:5-7 [Conf]
  14. Chung-Hsing Chen, Tanay Karnik, Daniel G. Saab
    Structural and behavioral synthesis for testability techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:6, pp:777-785 [Journal]
  15. Tanay Karnik, Peter Hazucha, Jagdish Patel
    Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Dependable Sec. Comput., 2004, v:1, n:2, pp:128-143 [Journal]
  16. Tanay Karnik, Peter Hazucha, Gerhard Schrom, Fabrice Paillet, Donald Gardner
    High-frequency DC-DC conversion : fact or fiction. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  17. Circuit techniques for dynamic variation tolerance. [Citation Graph (, )][DBLP]

  18. Resilient circuits - Enabling energy-efficient performance and reliability. [Citation Graph (, )][DBLP]

  19. Resilient microprocessor design for high performance & energy efficiency. [Citation Graph (, )][DBLP]

  20. Analytical Model for the Propagation Delay of Through Silicon Vias. [Citation Graph (, )][DBLP]

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