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Siva Narendra: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De
    Parameter variations and impact on circuits and microarchitecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:338-342 [Conf]
  2. James Kao, Siva Narendra, Anantha Chandrakasan
    MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:495-500 [Conf]
  3. Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
    Design optimizations for microprocessors at low temperature. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:2-5 [Conf]
  4. James Kao, Siva Narendra, Anantha Chandrakasan
    Subthreshold leakage modeling and reduction techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:141-148 [Conf]
  5. Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra
    Cascode buffer for monolithic voltage conversion operating at high input supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:464-467 [Conf]
  6. James Tschanz, Siva Narendra, Ali Keshavarzi, Vivek De
    Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:9-12 [Conf]
  7. Ali Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, T. Ghani, Shekhar Borkar, Vivek De
    Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:207-212 [Conf]
  8. Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
    Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:252-254 [Conf]
  9. Siva Narendra, Vivek De, Dimitri Antoniadis, Anantha Chandrakasan, Shekhar Borkar
    Scaling of stack effect and its application for leakage reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:195-200 [Conf]
  10. Siva Narendra, Vivek De, Shekhar Borkar, Dimitri Antoniadis, Anantha Chandrakasan
    Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:19-23 [Conf]
  11. Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald Gardner, Siva Narendra, Tanay Karnik, Vivek De
    Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:263-268 [Conf]
  12. Stephen Tang, Siva Narendra, Vivek De
    Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:199-204 [Conf]
  13. James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
    Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:147-152 [Conf]
  14. Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman
    Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:279-0 [Conf]
  15. Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman
    High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:517-521 [Conf]
  16. Ron Wilson, Siva Narendra, Vivek De
    Evening Panel Discussion: Process Variation: Is It Too Much to Handle? [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:213-0 [Conf]
  17. K. Narasimhulu, Siva Narendra, V. Ramgopal Rao
    The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:545-550 [Conf]
  18. Siva Narendra, Vasantha Erraguntla, James Tschanz, Nitin Borkar
    Design Challenges in Sub-100nm High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:15-17 [Conf]
  19. Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
    Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:36-43 [Journal]
  20. Siva Narendra
    Challenges and design choices in nanoscale CMOS. [Citation Graph (0, 0)][DBLP]
    JETC, 2005, v:1, n:1, pp:7-49 [Journal]
  21. Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, M. Stan, Vivek De
    Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:91-95 [Journal]

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