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Publications of Author

1. Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De
   Parameter variations and impact on circuits and microarchitecture. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:338-342 [Conf]
   
2. Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
   Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:486-491 [Conf]
   
3. James Tschanz, Keith A. Bowman, Vivek De
   Variation-tolerant circuits: circuit solutions and techniques. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:762-763 [Conf]
   
4. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
   Serial-link bus: a low-power on-chip bus architecture. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:541-546 [Conf]
   
5. Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
   A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:253-257 [Conf]
   
6. Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De
   Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:592-595 [Conf]
   
7. James Tschanz, Siva Narendra, Ali Keshavarzi, Vivek De
   Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:9-12 [Conf]
   
8. James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
   Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2001, pp:147-152 [Conf]
   
9. Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
   Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2006, pp:79-84 [Conf]
   
10. James Tschanz
    SUB 45nm Low Power Design Challenges. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:4- [Conf]
    
11. Gerhard Knoblinger, James Tschanz, Marcal Pol
    SUB-45nm Technology and Design Challenges. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:3- [Conf]
    
12. Siva Narendra, Vasantha Erraguntla, James Tschanz, Nitin Borkar
    Design Challenges in Sub-100nm High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:15-17 [Conf]
    
13. James Tschanz
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:378-379 [Conf]
    
14. Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
    Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:36-43 [Journal]
    
15. Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De
    Formal derivation of optimal active shielding for low-power on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:821-836 [Journal]
    
16. Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De
    Comparative Analysis of Conventional and Statistical Design Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:238-243 [Conf]
    
17. Ming Zhang, T. M. Mak, James Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu
    Design for Resilience to Soft Errors and Variations. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:23-28 [Conf]
    
18. Osman S. Unsal, James Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
    Impact of Parameter Variations on Circuits and Microarchitecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:6, pp:30-39 [Journal]
    
19. 
    Circuit techniques for dynamic variation tolerance. [Citation Graph (, )][DBLP]
    
    
20. 
    Resilient circuits - Enabling energy-efficient performance and reliability. [Citation Graph (, )][DBLP]