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Ali Keshavarzi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De
    Parameter variations and impact on circuits and microarchitecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:338-342 [Conf]
  2. Arman Vassighi, Ali Keshavarzi, Siva Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
    Design optimizations for microprocessors at low temperature. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:2-5 [Conf]
  3. José Luis Rosselló, V. Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
    A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:206-211 [Conf]
  4. Charles F. Hawkins, Ali Keshavarzi, Jaume Segura
    A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:267-0 [Conf]
  5. Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi
    Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:12-19 [Conf]
  6. Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi
    Thermal Management of High Performance Microprocessors. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:313-319 [Conf]
  7. James Tschanz, Siva Narendra, Ali Keshavarzi, Vivek De
    Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:9-12 [Conf]
  8. Ali Keshavarzi, Sean Ma, Siva Narendra, B. Bloechel, K. Mistry, T. Ghani, Shekhar Borkar, Vivek De
    Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:207-212 [Conf]
  9. Ali Keshavarzi, Siva Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
    Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:252-254 [Conf]
  10. Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De
    Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:26-29 [Conf]
  11. Kaushik Roy, Ali Keshavarzi
    Design and Test of Low Voltage CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:7- [Conf]
  12. B. Alorda, B. Bloechel, Ali Keshavarzi, Jaume Segura
    CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:719-726 [Conf]
  13. Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi
    Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1276-1284 [Conf]
  14. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1130-1139 [Conf]
  15. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1108-1117 [Conf]
  16. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins
    Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:146-155 [Conf]
  17. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, K. Soumyanath, Vivek De
    Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1051-1059 [Conf]
  18. Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins
    Parametric Failures in CMOS ICs - A Defect-Based Analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:90-99 [Conf]
  19. Oleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins
    Burn-in Temperature Projections for Deep Sub-micron Technologies. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:95-104 [Conf]
  20. Abhijit Chatterjee, A. Keshavarzi, Amit Patra, Siddhartha Mukhopadhyay
    Test Methodologies in the Deep Submicron Era -- Analog, Mixed-Signal, and RF. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:12-13 [Conf]
  21. Jaume Segura, Vivek De, Ali Keshavarzi
    Challenges in Nanometric Technology Scaling: Trends and Projections. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:447-448 [Conf]
  22. Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura
    Impact of Thermal Gradients on Clock Skew and Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:414-424 [Journal]
  23. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    DFT for Delay Fault Testing of High-Performance Digital Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:248-258 [Journal]
  24. Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
    IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:2, pp:24-33 [Journal]
  25. Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
    Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:36-43 [Journal]
  26. José Luis Rosselló, V. Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
    A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  27. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins
    Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:717-723 [Journal]
  28. Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, M. Stan, Vivek De
    Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:91-95 [Journal]
  29. Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Vivek De
    Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:863-870 [Journal]

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