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Soheil Ghiasi :
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Elaheh Bozorgzadeh , Soheil Ghiasi , Atsushi Takahashi , Majid Sarrafzadeh Optimal integer delay budgeting on directed acyclic graphs. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:920-925 [Conf ] Po-Kuan Huang , Soheil Ghiasi Leakage-aware intraprogram voltage scaling for embedded processors. [Citation Graph (0, 0)][DBLP ] DAC, 2006, pp:364-369 [Conf ] Po-Kuan Huang , Soheil Ghiasi Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities. [Citation Graph (0, 0)][DBLP ] DATE, 2006, pp:943-944 [Conf ] Elaheh Bozorgzadeh , Soheil Ghiasi , Atsushi Takahashi , Majid Sarrafzadeh Incremental Timing Budget Management in Programmable Systems. [Citation Graph (0, 0)][DBLP ] ERSA, 2004, pp:240-246 [Conf ] Soheil Ghiasi , Hyun J. Moon , Majid Sarrafzadeh Collaborative and Reconfigurable Object Tracking. [Citation Graph (0, 0)][DBLP ] Engineering of Reconfigurable Systems and Algorithms, 2003, pp:13-20 [Conf ] Soheil Ghiasi , Hyun J. Moon , Majid Sarrafzadeh Improving Performance and Quality thru Hardware Reconfiguration: Potentials and Adaptive Object Tracking Case Study. [Citation Graph (0, 0)][DBLP ] ESTImedia, 2003, pp:149-155 [Conf ] Jia Ming Mar , Alessandro Bissacco , Stefano Soatto , Soheil Ghiasi High Performance Feature Detection on a Reconfigurable Co-Processor. [Citation Graph (0, 0)][DBLP ] FCCM, 2006, pp:341-342 [Conf ] Soheil Ghiasi , Karlene Nguyen , Elaheh Bozorgzadeh , Majid Sarrafzadeh On computation and resource management in an FPGA-based computation environment. [Citation Graph (0, 0)][DBLP ] FPGA, 2003, pp:243- [Conf ] Taraneh Taghavi , Soheil Ghiasi , Majid Sarrafzadeh Routing algorithms: enhancing routability & enabling ECO (abstract only). [Citation Graph (0, 0)][DBLP ] FPGA, 2005, pp:266- [Conf ] Soheil Ghiasi , Elaheh Bozorgzadeh , Siddharth Choudhuri , Majid Sarrafzadeh A unified theory of timing budget management. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:653-659 [Conf ] Soheil Ghiasi Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:127-129 [Conf ] Taraneh Taghavi , Soheil Ghiasi , Abhishek Ranjan , Salil Raje , Majid Sarrafzadeh Innovate or perish: FPGA physical design. [Citation Graph (0, 0)][DBLP ] ISPD, 2004, pp:148-155 [Conf ] Soheil Ghiasi , Po-Kuan Huang Probabilistic Delay Budgeting for Soft Realtime Applications. [Citation Graph (0, 0)][DBLP ] ISQED, 2006, pp:141-146 [Conf ] Eren Kursun , Soheil Ghiasi , Majid Sarrafzadeh Transistor Level Budgeting for Power Optimization. [Citation Graph (0, 0)][DBLP ] ISQED, 2004, pp:116-121 [Conf ] Roozbeh Jafari , Hyduke Noshadi , Majid Sarrafzadeh , Soheil Ghiasi Adaptive Medical Feature Extraction for Resource Constrained Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] PerCom Workshops, 2006, pp:506-511 [Conf ] Elaheh Bozorgzadeh , Soheil Ghiasi , Atsushi Takahashi , Majid Sarrafzadeh Optimal integer delay-budget assignment on directed acyclic graphs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1184-1199 [Journal ] Soheil Ghiasi , Elaheh Bozorgzadeh , Po-Kuan Huang , Roozbeh Jafari , Majid Sarrafzadeh A Unified Theory of Timing Budget Management. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2364-2375 [Journal ] Soheil Ghiasi , Ani Nahapetian , Majid Sarrafzadeh An optimal algorithm for minimizing run-time reconfiguration delay. [Citation Graph (0, 0)][DBLP ] ACM Trans. Embedded Comput. Syst., 2004, v:3, n:2, pp:237-256 [Journal ] Soheil Ghiasi , Hyun J. Moon , Ani Nahapetian , Majid Sarrafzadeh Collaborative and Reconfigurable Object Tracking. [Citation Graph (0, 0)][DBLP ] The Journal of Supercomputing, 2004, v:30, n:3, pp:213-238 [Journal ] Xiaojian Yang , Maogang Wang , Ryan Kastner , Soheil Ghiasi , Majid Sarrafzadeh Congestion reduction during placement with provably good approximation bound. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:3, pp:316-333 [Journal ] Roozbeh Jafari , Hyduke Noshadi , Soheil Ghiasi , Majid Sarrafzadeh Adaptive Electrocardiogram Feature Extraction on Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Parallel Distrib. Syst., 2006, v:17, n:8, pp:797-807 [Journal ] Soheil Ghiasi , Po-Kuan Huang , Roozbeh Jafari Probabilistic delay budget assignment for synthesis of soft real-time applications. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2006, v:14, n:8, pp:843-853 [Journal ] Po-Kuan Huang , Soheil Ghiasi Efficient and scalable compiler-directed energy optimization for realtime applications. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:785-790 [Conf ] Taraneh Taghavi , Soheil Ghiasi , Majid Sarrafzadeh Routing algorithms: architecture driven rerouting enhancement for FPGAs. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Po-Kuan Huang , Matin Hashemi , Soheil Ghiasi Joint throughput and energy optimization for pipelined execution of embedded streaming applications. [Citation Graph (0, 0)][DBLP ] LCTES, 2007, pp:137-139 [Conf ] Roozbeh Jafari , Soheil Ghiasi , Majid Sarrafzadeh Medical Embedded Systems. [Citation Graph (0, 0)][DBLP ] IESS, 2007, pp:441-444 [Conf ] Po-Kuan Huang , Soheil Ghiasi Efficient and scalable compiler-directed energy optimization for realtime applications. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal ] Soheil Ghiasi An Effective Combinatorial Algorithm for Gate-Level Threshold Voltage Assignment. [Citation Graph (0, 0)][DBLP ] J. Low Power Electronics, 2006, v:2, n:3, pp:365-377 [Journal ] Soheil Ghiasi , Elaheh Bozorgzadeh , Karlene Nguyen , Majid Sarrafzadeh Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System. [Citation Graph (0, 0)][DBLP ] VLSI Signal Processing, 2006, v:42, n:1, pp:43-55 [Journal ] Exact and Approximate Task Assignment Algorithms for Pipelined Software Synthesis. [Citation Graph (, )][DBLP ] Incremental component implementation selection: enabling ECO in compositional system synthesis. [Citation Graph (, )][DBLP ] Look into details: the benefits of fine-grain streaming buffer analysis. [Citation Graph (, )][DBLP ] A programmable architecture for scalable and real-time network traffic measurements. [Citation Graph (, )][DBLP ] System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis. [Citation Graph (, )][DBLP ] Search in 0.014secs, Finished in 0.016secs