Search the dblp DataBase

Publications of Author

1. Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli
   Chameleon: a new multi-layer channel router. [Citation Graph (0, 0)][DBLP]
   DAC, 1986, pp:495-502 [Conf]
   
2. Venkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns
   The Effect of Wire Length Minimization on Yield. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:97-105 [Conf]
   
3. Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown
   A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:689-692 [Conf]
   
4. Vikas Chandra, Gary D. Carpenter, Jeff Burns
   Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. [Citation Graph (0, 0)][DBLP]
   ICCD, 2003, pp:134-139 [Conf]
   
5. Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
   Leakage and leakage sensitivity computation for combinational circuits. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:96-99 [Conf]
   
6. Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman
   A semi-custom voltage-island technique and its application to high-speed serial links. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:60-65 [Conf]
   
7. Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown
   Efficient techniques for gate leakage estimation. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:100-103 [Conf]
   
8. Jeffrey L. Burns, Jack A. Feldman
   C5M - a control logic layout synthesis system for high-performance microprocessors. [Citation Graph (0, 0)][DBLP]
   ISPD, 1997, pp:110-115 [Conf]
   
9. Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns
   Performance Driven Synthesis for Pass-Transistor Logic. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:372-377 [Conf]
   
10. Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
    Analysis and Optimization of Enhanced MTCMOS Scheme. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:234-239 [Conf]
    
11. Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma
    Techniques for multilayer channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:6, pp:698-712 [Journal]
    
12. Jeffrey L. Burns, Jack A. Feldman
    C5M-a control-logic layout synthesis system for high-performance microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:14-23 [Journal]