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Jianjiang Ceng: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr
    A novel approach for flexible and consistent ADL-driven ASIP design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:717-722 [Conf]
  2. Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini
    An integrated open framework for heterogeneous MPSoC design space exploration. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1145-1150 [Conf]
  3. Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    C Compiler Retargeting Based on Instruction Semantics Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1150-1155 [Conf]
  4. Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:463-473 [Conf]
  5. Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:33-46 [Conf]
  6. Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
    ASIP architecture exploration for efficient IPSec encryption: A case study. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]
  7. Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
    Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:235-246 [Journal]

  8. A high-level virtual platform for early MPSoC software development. [Citation Graph (, )][DBLP]


  9. TotalProf: a fast and accurate retargetable source code profiler. [Citation Graph (, )][DBLP]


  10. MAPS: an integrated framework for MPSoC application parallelization. [Citation Graph (, )][DBLP]


  11. Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. [Citation Graph (, )][DBLP]


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