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Zvonko G. Vranesic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic
    Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:427-432 [Conf]
  2. Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
    Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:227-233 [Conf]
  3. A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
    Design and Implementation of the NUMAchine Multiprocessor. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:66-69 [Conf]
  4. Muhammad Jaseemuddin, Zvonko G. Vranesic
    Bidirectional Ring: An Alternative to the Hierarchy of Unidirectional Rings. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1995, pp:567-578 [Conf]
  5. Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown
    A Multithreaded Soft Processor for SoPC Area Reduction. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:131-142 [Conf]
  6. Zeljko Zilic, Zvonko G. Vranesic
    Using BDDs to Design ULMs for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:24-30 [Conf]
  7. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Architecture of Centralized Field-Configurable Memory. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:97-103 [Conf]
  8. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:10-16 [Conf]
  9. Valavan Manohararajah, Terry Borer, Stephen Dean Brown, Zvonko G. Vranesic
    Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:232-241 [Conf]
  10. Sinisa Srbljic, Zvonko G. Vranesic, Leo Budin
    Performance Prediction for Different Consistency Schemes in Distributed Shared Memory Systems. [Citation Graph (0, 0)][DBLP]
    HPDC, 1994, pp:295-302 [Conf]
  11. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A Detailed Router for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:382-385 [Conf]
  12. Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic
    Technology Mapping on Lookup Table-Based FPGAs for Performance. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:568-571 [Conf]
  13. R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
    The NUMAchine Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:487-496 [Conf]
  14. Lap-kong Chan, Zvonko G. Vranesic
    TORMLAN - A Multichannel Local Area Network Protocol. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1990, pp:756-765 [Conf]
  15. Zvonko G. Vranesic, V. Carl Hamacher, A. K. Sanwalka, Safwat G. Zaky
    A Hybrid Token/Insertion Ring LAN. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1991, pp:211-220 [Conf]
  16. Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown
    Experiences with Soft-Core Processor Design. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  17. Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
    Memory-System Design Considerations for Dynamically-Scheduled Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1997, pp:133-143 [Conf]
  18. Zvonko G. Vranesic, V. Carl Hamacher, Y. Y. Leung
    Design of a Fully Variable - Length Structured Minicomputer. [Citation Graph (0, 0)][DBLP]
    ISCA, 1973, pp:251-255 [Conf]
  19. Alireza Kaviani, Zvonko G. Vranesic
    On Scheduling in Multiprocessor Systems Using Fuzzy Logic. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:141-147 [Conf]
  20. Konrad Lei, Zvonko G. Vranesic
    On the Synthesis of 4-Valued Current Mode CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1991, pp:147-155 [Conf]
  21. Konrad Lei, Zvonko G. Vranesic
    Towards the Realization of 4-Valued CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:104-110 [Conf]
  22. Zvonko G. Vranesic
    The FPGA Challenge. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1998, pp:121-0 [Conf]
  23. Safwat G. Zaky, Zvonko G. Vranesic, Mostafa H. Abd-El-Barr
    Step-Wise Synthesis of CCD MVL Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1990, pp:300-307 [Conf]
  24. Zeljko Zilic, Zvonko G. Vranesic
    Current-Mode CMOS Galois Field Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1993, pp:245-250 [Conf]
  25. Zeljko Zilic, Zvonko G. Vranesic
    Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:36-43 [Conf]
  26. Zeljko Zilic, Zvonko G. Vranesic
    New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1996, pp:16-23 [Conf]
  27. Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
    The Multicluster Architecture: Reducing Cycle Time Through Partitioning. [Citation Graph (0, 0)][DBLP]
    MICRO, 1997, pp:149-159 [Conf]
  28. Keith I. Farkas, Zvonko G. Vranesic, Michael Stumm
    Cache Consistency in Hierarchical-Ring-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:348-357 [Conf]
  29. Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic
    Reusable motion synthesis using state-space controllers. [Citation Graph (0, 0)][DBLP]
    SIGGRAPH, 1990, pp:225-234 [Conf]
  30. Steven J. E. Wilton, Zvonko G. Vranesic
    Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:51-55 [Conf]
  31. Zvonko G. Vranesic, V. Carl Hamacher
    Ternary logic in parallel multipliers. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1972, v:15, n:3, pp:254-258 [Journal]
  32. K. M. Waliuzzaman, Zvonko G. Vranesic
    On Decomposition of Multi-Valued Switching Functions. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1970, v:13, n:4, pp:359-362 [Journal]
  33. Wayne M. Loucks, William I. Kwak, Zvonko G. Vranesic
    Implementation of a Dynamic Address Assignment Protocol in a Local Area Network. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 1986, v:11, n:, pp:133-146 [Journal]
  34. Zvonko G. Vranesic, Michael Stumm, David M. Lewis, Ron White
    Hector: A Hierarchically Structured Shared-memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:72-79 [Journal]
  35. Michiel van de Panne, Eugene Fiume, Zvonko G. Vranesic
    Physically Based Modeling and Control of Turning. [Citation Graph (0, 0)][DBLP]
    CVGIP: Graphical Model and Image Processing, 1993, v:55, n:6, pp:507-521 [Journal]
  36. Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic
    Minimizing FPGA Interconnect Delays. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:16-23 [Journal]
  37. Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic
    The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 1999, v:27, n:5, pp:327-356 [Journal]
  38. C. L. Lam, Zvonko G. Vranesic
    Key compression using segment strings. [Citation Graph (0, 0)][DBLP]
    Inf. Syst., 1981, v:6, n:2, pp:139-146 [Journal]
  39. Mostafa H. Abd-El-Barr, Zvonko G. Vranesic
    Cost Reduction in the CCD Realization of MVMT Function. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:5, pp:702-706 [Journal]
  40. Mostafa H. Abd-El-Barr, Zvonko G. Vranesic, Safwat G. Zaky
    Algorithmic Synthesis of MVL Functions for CCD Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:8, pp:977-986 [Journal]
  41. Mostafa H. Abd-El-Barr, Safwat G. Zaky, Zvonko G. Vranesic
    Synthesis of Multivalued Multithreshold Functions for CCD Implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:2, pp:124-133 [Journal]
  42. Kuang-Wei Chiang, Zvonko G. Vranesic
    A Tree Representation of Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:3, pp:315-319 [Journal]
  43. Kuang-Wei Chiang, Zvonko G. Vranesic
    Comments on ``Fault Diagnosis of MOS Combinational Networks''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:10, pp:947- [Journal]
  44. Paul Chow, Zvonko G. Vranesic, Jui Lin Yen
    A Pipelined Distributed Arithmetic PFFT Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:12, pp:1128-1136 [Journal]
  45. A. Druzeta, Zvonko G. Vranesic
    A. Higher Radix Technique for Fault Detection in Many-Valued Multithreshold Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:11, pp:1070-1073 [Journal]
  46. H. T. Mouftah, K. C. Smith, Zvonko G. Vranesic
    Ternary Rate-Multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1980, v:29, n:10, pp:929-931 [Journal]
  47. Sinisa Srbljic, Zvonko G. Vranesic, Michael Stumm, Leo Budin
    Analytical Prediction of Performance for Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:11, pp:1155-1173 [Journal]
  48. Zvonko G. Vranesic
    Multiple-Valued Logic: An Introduction and Overview. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1977, v:26, n:12, pp:1181-1182 [Journal]
  49. Zeljko Zilic, Zvonko G. Vranesic
    A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:9, pp:1100-1105 [Journal]
  50. Zeljko Zilic, Zvonko G. Vranesic
    A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:8, pp:1012-1020 [Journal]
  51. Zeljko Zilic, Zvonko G. Vranesic
    Using Decision Diagrams to Design ULMs for FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:9, pp:970-982 [Journal]
  52. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A detailed router for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:5, pp:620-628 [Journal]
  53. Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic
    A stochastic model to predict the routability of field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1827-1838 [Journal]
  54. Debatosh Debnath, Zvonko G. Vranesic
    A fast algorithm for OR-AND-OR synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1166-1176 [Journal]
  55. Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
    Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2331-2340 [Journal]
  56. Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic
    Parallel standard cell placement algorithms with quality equivalent to simulated annealing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:3, pp:387-396 [Journal]
  57. Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
    Adaptive FPGAs: High-Level Architecture and a Synthesis Method. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  58. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    The memory/logic interface in FPGAs with large embedded memory arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:80-91 [Journal]
  59. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Structural analysis and generation of synthetic digital circuits with memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:223-226 [Journal]

  60. Enhancements to FPGA design methodology using streaming. [Citation Graph (, )][DBLP]


  61. On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. [Citation Graph (, )][DBLP]


  62. Towards Compilation of Streaming Programs into FPGA Hardware. [Citation Graph (, )][DBLP]


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