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Stephen W. Director: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michael L. Bushnell, Stephen W. Director
    VLSI CAD tool integration using the Ulysses environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:55-61 [Conf]
  2. Juan Antonio Carballo, Stephen W. Director
    Application of Constraint-Based Heuristics in Collaborative Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:395-400 [Conf]
  3. Juan Antonio Carballo, Stephen W. Director
    Constraint Management for Collaborative Electronic Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:529-534 [Conf]
  4. James Daniell, Stephen W. Director
    An Object Oriented Approach to CAD Tool Control within a Design Framework. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:197-202 [Conf]
  5. John W. Hagerman, Stephen W. Director
    Improved Tool and Data Selection in Task Management. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:181-184 [Conf]
  6. Margarida F. Jacome, Stephen W. Director
    Design Process Management for CAD Frameworks. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:500-505 [Conf]
  7. Vladimir Koval, Igor W. Farmaga, Andrzej J. Strojwas, Stephen W. Director
    MONSTR: A Complete Thermal Simulator of Electronic Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:570-575 [Conf]
  8. Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director
    Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:535-540 [Conf]
  9. Peter R. Sutton, Jay B. Brockman, Stephen W. Director
    Design Management Using Dynamically Defined Flows. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:648-653 [Conf]
  10. Peter R. Sutton, Stephen W. Director
    A Description Language for Design Process Management. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:175-180 [Conf]
  11. Peter R. Sutton, Stephen W. Director
    Framework Encapsulations: A New Approach to CAD Tool Interoperability. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:134-139 [Conf]
  12. M. T. Trick, Stephen W. Director
    LASSIE: Structure to Layout for Behavioral Synthesis Tools. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:104-109 [Conf]
  13. Luís M. Vidigal, Sani R. Nassif, Stephen W. Director
    CINNAMON: coupled integration and nodal analysis of MOS networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:179-185 [Conf]
  14. Tariq Samad, Stephen W. Director
    Towards a natural language interface for CAD. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:2-8 [Conf]
  15. Jingyan Zuo, Stephen W. Director
    An Integrated Design Environment for Early Stage Conceptual Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:754- [Conf]
  16. Zhihua Wang, Stephen W. Director
    An Efficient Yield Optimization Method Using A Two Step Linear Approximation of Circuit Performance. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:567-571 [Conf]
  17. Jay B. Brockman, Stephen W. Director
    The Hercules CAD Task Management System. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:254-257 [Conf]
  18. Stephen W. Director, Jonathan Allen, J. Duley
    Engineering education: trends and needs (panel). [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:456- [Conf]
  19. Peter Feldmann, Stephen W. Director
    Accurate and Efficient Evaluation of Circuit Yield and Yield Gradients. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:120-123 [Conf]
  20. Peter Feldmann, Stephen W. Director
    Improved Methods for IC Yield and Quality Optimization Using Surface Integrals. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:158-161 [Conf]
  21. Margarida F. Jacome, Stephen W. Director
    A formal basis for design process planning and management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:516-521 [Conf]
  22. Kannan Krishna, Stephen W. Director
    A novel methodology for statistical parameter extraction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:696-699 [Conf]
  23. Jay B. Brockman, Stephen W. Director
    A Schema-Based Approach to CAD Task Management. [Citation Graph (0, 0)][DBLP]
    Electronic Design Automation Frameworks, 1992, pp:71-84 [Conf]
  24. Michael L. Bushnell, Stephen W. Director
    ULYSSES - a knowledge-based VLSI design environment. [Citation Graph (0, 0)][DBLP]
    AI in Engineering, 1987, v:2, n:1, pp:33-41 [Journal]
  25. Jay B. Brockman, Stephen W. Director
    The schema-based approach to workflow management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:10, pp:1257-1267 [Journal]
  26. Michael L. Bushnell, Stephen W. Director
    Automated design tool execution in the Ulysses design environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:279-287 [Journal]
  27. James Daniell, Stephen W. Director
    An object oriented approach to CAD tool control [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:698-713 [Journal]
  28. Peter Feldmann, Stephen W. Director
    Integrated circuit quality optimization using surface integrals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:12, pp:1868-1879 [Journal]
  29. Peter Feldmann, Tuyen V. Nguyen, Stephen W. Director, Ronald A. Rohrer
    Sensitivity computation in piecewise approximate circuit simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:2, pp:171-183 [Journal]
  30. Margarida F. Jacome, Stephen W. Director
    A formal basis for design process planning and management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1197-1210 [Journal]
  31. Kannan Krishna, Stephen W. Director
    The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1557-1568 [Journal]
  32. K. K. Low, Stephen W. Director
    An efficient methodology for building macromodels of IC fabrication processes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1299-1313 [Journal]
  33. K. K. Low, Stephen W. Director
    A new methodology for the design centering of IC fabrication processes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:895-903 [Journal]
  34. Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director
    VLSI Yield Prediction and Estimation: A Unified Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:114-130 [Journal]
  35. Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
    FABRICS II: A Statistically Based IC Fabrication Process Simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:1, pp:40-46 [Journal]
  36. Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director
    A Methodology for Worst-Case Analysis of Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:104-113 [Journal]
  37. David P. La Potin, Stephen W. Director
    Mason: A Global Floorplanning Approach for VLSI Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:477-489 [Journal]
  38. Karem A. Sakallah, Stephen W. Director
    SAMSON2: An Event Driven VLSI Circuit Simulator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:4, pp:668-684 [Journal]
  39. Costas J. Spanos, Stephen W. Director
    Parameter Extraction for Statistical IC Process Characterization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:66-78 [Journal]
  40. Andrzej J. Strojwas, Stephen W. Director
    A Pattern Recognition Based Method for IC Failure Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:1, pp:76-92 [Journal]
  41. Andrzej J. Strojwas, Stephen W. Director
    An efficient algorithm for parametric fault simulation of monolithic IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1049-1058 [Journal]
  42. Luís M. Vidigal, Stephen W. Director
    A Design Centering Algorithm for Nonconvex Regions of Acceptability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1982, v:1, n:1, pp:13-24 [Journal]
  43. D. M. H. Walker, Stephen W. Director
    VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:4, pp:541-556 [Journal]

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