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Kenneth M. Butler: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kenneth M. Butler, M. Ray Mercer
    The Influences of Fault Type and Topology on Fault Model Performance and the Implications to Test and Testable Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:673-678 [Conf]
  2. Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer
    Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:417-420 [Conf]
  3. Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler
    CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:597-600 [Conf]
  4. Hari Balachandran, Kenneth M. Butler, Neil Simpson
    Facilitating Rapid First Silicon Debug. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:628-637 [Conf]
  5. Hari Balachandran, Jason Parker, Gordon Gammie, John W. Olson, Craig Force, Kenneth M. Butler, Sri Jandhyala
    Expediting ramp-to-volume production. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:103-112 [Conf]
  6. Hari Balachandran, Jason Parker, Daniel Shupp, Stephanie Butler, Kenneth M. Butler, Craig Force, Jason Smith
    Correlation of logical failures to a suspect process step. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:458-476 [Conf]
  7. Kenneth M. Butler
    Is ITC Bored with Board Test? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1237- [Conf]
  8. Kenneth M. Butler
    Sure You Can Get to 100 DPPM in Deep Submicron, But It'll Cost Ya. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1419- [Conf]
  9. Kenneth M. Butler
    Deep Submicron: Is Test Up to the Challenge? [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:923- [Conf]
  10. Kenneth M. Butler
    The stuck-at fault: it ain't over 'til it's over. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1165- [Conf]
  11. Kenneth M. Butler
    Stuck-at fault: a fault model for the next millennium. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1166- [Conf]
  12. Kenneth M. Butler
    A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:839-847 [Conf]
  13. Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Jones, Jayashree Saxena
    Integrating Automated Diagnosis into the Testing and Failure Analysis Operations. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:934- [Conf]
  14. Kenneth M. Butler, Jayashree Saxena, Tony Fryars, Graham Hetherington
    Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:355-364 [Conf]
  15. Graham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell
    Test Generation and Design for Test for a Large Multiprocessing DSP. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:149-156 [Conf]
  16. Frank F. Hsu, Kenneth M. Butler, Janak H. Patel
    A case study on the implementation of the Illinois Scan Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:538-547 [Conf]
  17. David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler
    Bridging Fault Diagnosis in the Absence of Physical Information. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:887-893 [Conf]
  18. Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly
    So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1037-1038 [Conf]
  19. Jayashree Saxena, Kenneth M. Butler
    An empirical study on the effects of test type ordering on overall test efficiency. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:408-416 [Conf]
  20. Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess
    On applying non-classical defect models to automated diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:748-757 [Conf]
  21. Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech
    Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges . [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1120-1129 [Conf]
  22. Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger
    A Case Study of IR-Drop in Structured At-Speed Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1098-1104 [Conf]
  23. Jayashree Saxena, Kenneth M. Butler, Lee Whetsel
    An analysis of power reduction techniques in scan testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:670-677 [Conf]
  24. Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler
    Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:729-738 [Conf]
  25. Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken
    An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:459- [Conf]
  26. Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer
    REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experimen. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:268-274 [Conf]
  27. Kenneth M. Butler
    Guest Editor's Introduction: ITC Helps Get More Out of Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:5, pp:388-389 [Journal]
  28. Kenneth M. Butler
    Estimating the Economic Benefits of DFT. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1999, v:16, n:1, pp:71-79 [Journal]
  29. Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang
    Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:6-7 [Journal]
  30. Kenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Kinra, Jayashree Saxena
    Automated Diagnosis in Testing and Failure Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:3, pp:83-89 [Journal]
  31. Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang
    Defect-Oriented Testing and Defective-Part-Level Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:1, pp:31-41 [Journal]

  32. Adapting to adaptive testing. [Citation Graph (, )][DBLP]


  33. Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs. [Citation Graph (, )][DBLP]


  34. Multidimensional Test Escape Rate Modeling. [Citation Graph (, )][DBLP]


  35. Power Supply Noise: A Survey on Effects and Research. [Citation Graph (, )][DBLP]


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