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Don E. Ross: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer
    Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:417-420 [Conf]
  2. Rhonda Kay Gaede, Don E. Ross, M. Ray Mercer, Kenneth M. Butler
    CATAPULT: Concurrent Automatic Testing Allowing Parallelization and Using Limited Topology. [Citation Graph (0, 0)][DBLP]
    DAC, 1988, pp:597-600 [Conf]
  3. M. Ray Mercer, Rohit Kapur, Don E. Ross
    Functional Approaches to Generating Orderings for Efficient Symbolic Representations. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:624-627 [Conf]
  4. Sherif H. K. Embabi, R. Damodaran, R. Bhagwan, Don E. Ross
    An Accurate Delay Model for BiCMOS Gates and Off-chip Drivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1539-1542 [Conf]
  5. Don E. Ross, Tim Wood, Grady Giles
    Conversion of small functional test sets of nonscan blocks to scan patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:691-700 [Conf]
  6. Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross
    Efficient variable ordering and partial representation algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:81-86 [Conf]
  7. Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk
    Memory BIST Using ESP. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:243-248 [Conf]
  8. Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama
    Built-in self test for C-testable ILA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1388-1398 [Journal]

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