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Publications of Author

1. Srihari Cadambi, Chandra Mulpuri, Pranav Ashar
   A fast, inexpensive and scalable hardware acceleration technique for functional simulation. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:570-575 [Conf]
   
2. Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu
   Signature-based workload estimation for mobile 3D graphics. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:592-597 [Conf]
   
3. Bren Mochocki, Kanishka Lahiri, Srihari Cadambi
   Power analysis of mobile 3D graphics. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:502-507 [Conf]
   
4. Srihari Cadambi, Seth Copen Goldstein
   CPR: A Configuration Profiling Tool. [Citation Graph (0, 0)][DBLP]
   FCCM, 1999, pp:104-113 [Conf]
   
5. Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas
   Managing Pipeline-Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 1998, pp:55-64 [Conf]
   
6. Srihari Cadambi, Seth Copen Goldstein
   Static Profile-Driven Compilation for FPGAs. [Citation Graph (0, 0)][DBLP]
   FPL, 2001, pp:112-122 [Conf]
   
7. Srihari Cadambi, Seth Copen Goldstein
   Efficient Place and Route for Pipeline Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
   ICCD, 2000, pp:423-429 [Conf]
   
8. Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, Ronald Laufer
   PipeRench: A Coprocessor for Streaming multimedia Acceleration. [Citation Graph (0, 0)][DBLP]
   ISCA, 1999, pp:28-39 [Conf]
   
9. Jahangir Hasan, Srihari Cadambi, Venkata Jakkula, Srimat T. Chakradhar
   Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture. [Citation Graph (0, 0)][DBLP]
   ISCA, 2006, pp:203-215 [Conf]
   
10. Seth Copen Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matthew Moe, R. Reed Taylor
    PipeRench: A Reconfigurable Architecture and Compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:4, pp:70-77 [Journal]
    
11. Michela Becchi, Srihari Cadambi
    Memory-Efficient Regular Expression Search Using State Merging. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 2007, pp:1064-1072 [Conf]
    
12. 
    A Massively Parallel Coprocessor for Convolutional Neural Networks. [Citation Graph (, )][DBLP]
    
    
13. 
    Best-effort semantic document search on GPUs. [Citation Graph (, )][DBLP]
    
    
14. 
    A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines. [Citation Graph (, )][DBLP]
    
    
15. 
    Using hardware transactional memory for data race detection. [Citation Graph (, )][DBLP]
    
    
16. 
    A dynamically configurable coprocessor for convolutional neural networks. [Citation Graph (, )][DBLP]
    
    
17. 
    A Massively Parallel Digital Learning Processor. [Citation Graph (, )][DBLP]
    
    
18. 
    RaceTM: detecting data races using transactional memory. [Citation Graph (, )][DBLP]
    
    
19. 
    Data-aware scheduling of legacy kernels on heterogeneous platforms with distributed memory. [Citation Graph (, )][DBLP]
    
    
20. 
    Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. [Citation Graph (, )][DBLP]