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Pak K. Chan :
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Pak K. Chan , Kevin Karplus Computing Signal Delay in General RC Networks by Tree/Link Partitioning. [Citation Graph (0, 0)][DBLP ] DAC, 1989, pp:485-490 [Conf ] Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien On Routability Prediction for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:326-330 [Conf ] Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien Spectral K -Way Ratio-Cut Partitioning and Clustering. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:749-754 [Conf ] Pak K. Chan Algorithms for Library-Specific Sizing of Combinational Logic. [Citation Graph (0, 0)][DBLP ] DAC, 1990, pp:353-356 [Conf ] Pak K. Chan , Mark J. Boyd , S. Goren , K. Klenk , V. Kodavati , R. Kundu , M. Margolese , J. Sun , K. Suzuki , E. Thorne , X. Wang , J. Xu , M. Zhu Reducing Compilation Time of Zhong's FPGA-Based SAT Solver. [Citation Graph (0, 0)][DBLP ] FCCM, 1999, pp:308-309 [Conf ] Pak K. Chan , Martine D. F. Schlag Acceleration of an FPGA router. [Citation Graph (0, 0)][DBLP ] FCCM, 1997, pp:175-181 [Conf ] Pak K. Chan , Martine D. F. Schlag New parallelization and convergence results for NC: a negotiation-based FPGA router. [Citation Graph (0, 0)][DBLP ] FPGA, 2000, pp:165-174 [Conf ] Pak K. Chan , Martine D. F. Schlag Parallel placement for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP ] FPGA, 2003, pp:43-50 [Conf ] Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien Spectral-Based Multi-Way FPGA Partitioning. [Citation Graph (0, 0)][DBLP ] FPGA, 1995, pp:133-139 [Conf ] Jason Y. Zien , Pak K. Chan , Martine D. F. Schlag Hybrid spectral/iterative partitioning. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:436-440 [Conf ] Jason Y. Zien , Martine D. F. Schlag , Pak K. Chan Multi-level spectral hypergraph partitioning with arbitrary vertex sizes. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:201-204 [Conf ] Martine D. F. Schlag , Jackson Kong , Pak K. Chan Routability-Driven Techology Mapping for LookUp-Table-Based FPGAs. [Citation Graph (0, 0)][DBLP ] ICCD, 1992, pp:86-90 [Conf ] Pak K. Chan , Martine D. F. Schlag Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1990, v:39, n:8, pp:983-992 [Journal ] Pak K. Chan , Martine D. F. Schlag , Clark D. Thomborson , Vojin G. Oklobdzija Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1992, v:41, n:8, pp:920-930 [Journal ] Pak K. Chan Comments on `Asymptotic waveform evaluation for timing analysis'. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1078-1079 [Journal ] Pak K. Chan , Kevin Karplus Computing signal delay in general RC networks by tree/link partitioning. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:8, pp:898-902 [Journal ] Pak K. Chan , Martine D. F. Schlag Bounds on signal delay in RC mesh networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:581-589 [Journal ] Pak K. Chan , Martine D. F. Schlag , Carl Ebeling , Larry McMurchie Distributed-memory parallel routing for field-programmable gatearrays. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:850-862 [Journal ] Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien Spectral K-way ratio-cut partitioning and clustering. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:9, pp:1088-1096 [Journal ] Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien Spectral-based multiway FPGA partitioning. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:5, pp:554-560 [Journal ] Martine D. F. Schlag , Pak K. Chan , Jackson Kong Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:713-722 [Journal ] Martine D. F. Schlag , Jackson Kong , Pak K. Chan Routability-driven technology mapping for lookup table-based FPGA's. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:13-26 [Journal ] Jason Y. Zien , Martine D. F. Schlag , Pak K. Chan Multilevel spectral hypergraph partitioning with arbitrary vertex sizes. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1389-1399 [Journal ] Search in 0.002secs, Finished in 0.305secs