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Paul Six: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. H. Cai, Stefaan Note, Paul Six, Hugo De Man
    A Data Path Layout Assembler for High Performance DSP Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:306-311 [Conf]
  2. Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes, Sven Wuytack, Gjalt G. de Jong, Francky Catthoor, Diederik Verkest, Paul Six, Hugo De Man
    Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:76-81 [Conf]
  3. Paul Six, Luc J. M. Claesen, Jan M. Rabaey, Hugo De Man
    An intelligent module generator environment. [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:730-735 [Conf]
  4. I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
    REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:694-697 [Conf]
  5. Evagelos Katsadas, Z. Sahraoui, M. Wouters, Veerle Derudder, Ivo Bolsens, Paul Six, Hugo De Man
    Regular Module Generation or Standard Cells: Two Alternative Implementations of a Library of Functional Building Blocks. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:167-181 [Conf]
  6. Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man
    Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:61-71 [Conf]
  7. I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man
    REDUSA: module generation by automatic elimination of superfluous blocks in regular structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:989-998 [Journal]
  8. Paul Vanoostende, Paul Six, Hugo De Man
    DARSI: RC data reduction [VLSI simulation]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:4, pp:493-500 [Journal]

  9. Timing optimization by bit-level arithmetic transformations. [Citation Graph (, )][DBLP]


  10. Search space reduction through clustering in test generation. [Citation Graph (, )][DBLP]


  11. CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler. [Citation Graph (, )][DBLP]


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