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Stefanus Mantik: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
    Effective Iterative Techniques for Fingerprinting Design IP. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:843-848 [Conf]
  2. Stephen Fenstermaker, David George, Andrew B. Kahng, Stefanus Mantik, Bart Thielges
    METRICS: a system architecture for design process optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:705-710 [Conf]
  3. Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Watermarking Techniques for Intellectual Property Protection. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:776-781 [Conf]
  4. Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Robust IP Watermarking Methodologies for Physical Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:782-787 [Conf]
  5. Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, Miodrag Potkonjak, Jennifer L. Wong
    Copy detection for intellectual property protection of VLSI designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:600-605 [Conf]
  6. Andrew B. Kahng, Stefanus Mantik
    On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:17-21 [Conf]
  7. Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
    On wirelength estimations for row-based placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:4-11 [Conf]
  8. Andrew B. Kahng, Stefanus Mantik, Igor L. Markov
    Min-max placement for large-scale timing optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:143-148 [Conf]
  9. Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt
    Requirements for models of achievable routing. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:4-11 [Conf]
  10. Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
    A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:339-343 [Conf]
  11. Andrew B. Kahng, Stefanus Mantik
    A System for Automatic Recording and Prediction of Design Quality Metrics. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:81-86 [Conf]
  12. Andrew B. Kahng, Stefanus Mantik
    Measurement of Inherent Noise in EDA Tools. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:206-212 [Conf]
  13. Kenneth D. Boese, Andrew B. Kahng, Stefanus Mantik
    On the relevance of wire load models. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:91-98 [Conf]
  14. Andrew E. Caldwell, Hyun-Jin Choi, Andrew B. Kahng, Stefanus Mantik, Miodrag Potkonjak, Gang Qu, Jennifer L. Wong
    Effective iterative techniques for fingerprinting design IP. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:208-215 [Journal]
  15. Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky
    On wirelength estimations for row-based placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1265-1278 [Journal]
  16. Andrew B. Kahng, John Lach, William H. Mangione-Smith, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak, Paul Tucker, Huijuan Wang, Gregory Wolfe
    Constraint-based watermarking techniques for design IP protection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1236-1252 [Journal]
  17. Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt
    Toward accurate models of achievable routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:648-659 [Journal]
  18. Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
    Routing-aware scan chain ordering. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:546-560 [Journal]

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