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Bradley S. Carlson :
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Bradley S. Carlson , C. Y. Roger Chen Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering. [Citation Graph (0, 0)][DBLP ] DAC, 1993, pp:361-366 [Conf ] Bradley S. Carlson , C. Y. Roger Chen , Dikran S. Meliksetian Transistor Chaining in CMOS Leaf Cells of Planar Topology. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1996, pp:194-199 [Conf ] Hung-Jung Chen , Bradley S. Carlson Power estimation for a submicron CMOS inverter driving a CRC interconnect load. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2000, pp:162-166 [Conf ] Harry Hollander , Bradley S. Carlson , Toby D. Bennett Synthesis of SEU-tolerant ASICs using concurrent error correction. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1995, pp:90-93 [Conf ] Yuan Hu , Ahmed Ghouse , Bradley S. Carlson Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow Graphs. [Citation Graph (0, 0)][DBLP ] ICCD, 1993, pp:21-24 [Conf ] Zhang Zhu , Bradley S. Carlson Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family. [Citation Graph (0, 0)][DBLP ] ICCD, 1997, pp:732-737 [Conf ] Yuan Hu , Bradley S. Carlson A Unified Algorithm for Estimation and Scheduling in Data Path Synthesis. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:57-60 [Conf ] Yuan Hu , Bradley S. Carlson Improved Lower Bounds for the Scheduling Optimization Problem. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:295-298 [Conf ] Bradley S. Carlson Principles vs. Practices in Undergraduate Microelectronic Systems Education. [Citation Graph (0, 0)][DBLP ] MSE, 2001, pp:22-23 [Conf ] Bradley S. Carlson , C. Y. Roger Chen , Dikran S. Meliksetian Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology. [Citation Graph (0, 0)][DBLP ] Discrete Applied Mathematics, 1999, v:90, n:1-3, pp:89-114 [Journal ] Bradley S. Carlson , C. Y. Roger Chen , Dikran S. Meliksetian Dual Eulerian Properties of Plane Multigraphs. [Citation Graph (0, 0)][DBLP ] SIAM J. Discrete Math., 1995, v:8, n:1, pp:33-50 [Journal ] N. W. Lo , Bradley S. Carlson , D. L. Tao Fault Tolerant Algorithms for Broadcasting on the Star Graph Network. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1997, v:46, n:12, pp:1357-1362 [Journal ] Bradley S. Carlson , C. Y. Roger Chen , Uminder Singh Optimal cell generation for dual independent layout styles. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:770-782 [Journal ] Bradley S. Carlson , Suh-Juch Lee Delay optimization of digital CMOS VLSI circuits by transistor reordering. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:10, pp:1183-1192 [Journal ] C. Y. Roger Chen , Cliff Yungchin Hou , Bradley S. Carlson A preprocessor for improving channel routing hierarchical pin permutation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:7, pp:896-903 [Journal ] Qinghong Wu , C. Y. Roger Chen , Bradley S. Carlson LILA: layout generation for iterative logic arrays. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1359-1369 [Journal ] Maciek Kormicki , Ausif Mahmood , Bradley S. Carlson Parallel logic simulation on a network of workstations using parallel virtual machine. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:2, pp:123-134 [Journal ] Search in 0.002secs, Finished in 0.002secs