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Mario R. Casu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mario R. Casu, Luca Macchiarulo
    A new approach to latency insensitive design. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:576-581 [Conf]
  2. Mario R. Casu, Luca Macchiarulo
    Issues in Implementing Latency Insensitive Protocols. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1390-1391 [Conf]
  3. Mario R. Casu, Luca Macchiarulo
    A New System Design Methodology for Wire Pipelined SoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:944-945 [Conf]
  4. Sergio Tota, Mario R. Casu, Luca Macchiarulo
    Implementation analysis of NoC: a MPSoC trace-driven approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:204-209 [Conf]
  5. Mario R. Casu, Luca Macchiarulo
    On-Chip Transparent Wire Pipelining. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:160-167 [Conf]
  6. Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
    Synthesis of low-leakage PD-SOI circuits with body-biasing. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:287-290 [Conf]
  7. Mario R. Casu, Luca Macchiarulo
    Floorplanning for throughput. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:62-69 [Conf]
  8. Mario R. Casu, Luca Macchiarulo
    Floorplan assisted data rate enhancement through wire pipelining: a real assessment. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:121-128 [Conf]
  9. Mario R. Casu, Philippe Flatresse
    Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. [Citation Graph (0, 0)][DBLP]
    MTDT, 2002, pp:163-167 [Conf]
  10. Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
    Effects of Temperature in Deep-Submicron Global Interconnect Optimization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:90-100 [Conf]
  11. M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:121-130 [Conf]
  12. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni
    Clock Distribution Network Optimization under Self-Heating and Timing Constraints. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:198-208 [Conf]
  13. Mario R. Casu, Luca Macchiarulo
    Throughput-driven floorplanning with wire pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:663-675 [Journal]
  14. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    An electromigration and thermal model of power wires for a priori high-level reliability prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:349-358 [Journal]
  15. Mario R. Casu, Giuseppe Durisi
    Implementation aspects of a transmitted-reference UWB receiver. [Citation Graph (0, 0)][DBLP]
    Wireless Communications and Mobile Computing, 2005, v:5, n:5, pp:537-549 [Journal]
  16. Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2004, v:35, n:10, pp:849-857 [Journal]
  17. Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
    An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1424-1429 [Conf]
  18. Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
    Coupled electro-thermal modeling and optimization of clock networks. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:12, pp:1175-1185 [Journal]

  19. A flexible UWB Transmitter for breast cancer detection imaging systems. [Citation Graph (, )][DBLP]


  20. MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. [Citation Graph (, )][DBLP]


  21. Adaptive Latency-Insensitive Protocols. [Citation Graph (, )][DBLP]


  22. Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis. [Citation Graph (, )][DBLP]


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