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Yajun Ran: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Temporofunctional crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:860-863 [Conf]
  2. Yajun Ran, Malgorzata Marek-Sadowska
    Crosstalk noise in FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:944-949 [Conf]
  3. Yajun Ran, Malgorzata Marek-Sadowska
    On designing via-configurable cell blocks for regular fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:198-203 [Conf]
  4. Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Eliminating False Positives in Crosstalk Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1192-1197 [Conf]
  5. Yajun Ran, Malgorzata Marek-Sadowska
    An integrated design flow for a via-configurable gate array. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:582-589 [Conf]
  6. Yajun Ran, Malgorzata Marek-Sadowska
    Via-configurable routing architectures and fast design mappability estimation for regular fabrics. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:25-32 [Conf]
  7. Yajun Ran, Malgorzata Marek-Sadowska
    The Magic of a Via-Configurable Regular Fabric. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:338-343 [Conf]
  8. Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Eliminating false positives in crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1406-1419 [Journal]
  9. Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska
    General skew constrained clock network sizing based on sequential linear programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:773-782 [Journal]
  10. Yajun Ran, Malgorzata Marek-Sadowska
    Designing via-configurable logic blocks for regular fabric. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:1-14 [Journal]
  11. Yajun Ran, Malgorzata Marek-Sadowska
    Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:998-1009 [Journal]

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