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Publications of Author

1. Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler
   Sequential Circuit Delay optimization Using Global Path Delays. [Citation Graph (0, 0)][DBLP]
   DAC, 1993, pp:483-489 [Conf]
   
2. Chia-Jeng Tseng, Ruey-Sing Wei, Steven G. Rothweiler, Michael M. Tong, Ajoy K. Bose
   Bridge: A Versatile Behavioral Synthesis System. [Citation Graph (0, 0)][DBLP]
   DAC, 1988, pp:415-420 [Conf]
   
3. Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou
   BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. [Citation Graph (0, 0)][DBLP]
   DAC, 1988, pp:409-414 [Conf]
   
4. Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler
   Performance optimization of sequential circuits by eliminating retiming bottlenecks. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1992, pp:504-509 [Conf]
   
5. Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler
   Deriving Signal Constraints to Accelerate Sequential Test Generation. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1997, pp:488-494 [Conf]
   
6. Srimat T. Chakradhar, Steven G. Rothweiler
   Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. [Citation Graph (0, 0)][DBLP]
   VTS, 1995, pp:12-19 [Conf]
   
7. Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler
   A transitive closure algorithm for test generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:1015-1028 [Journal]
   
8. Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal
   Redundancy removal and test generation for circuits with non-Boolean primitives. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1370-1377 [Journal]