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Chih-Wei Jim Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska
    Fast post-placement rewiring using easily detectable functional symmetries. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:286-289 [Conf]
  2. Chih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska
    Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:97-102 [Conf]
  3. Chih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska
    In-place delay constrained power optimization using functional symmetries. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:377-382 [Conf]
  4. Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
    Who are the alternative wires in your neighborhood? (alternative wires identification without search). [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:103-108 [Conf]
  5. Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
    Single-Pass Redundancy Addition and Removal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:606-609 [Conf]
  6. Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
    ATPG-based logic synthesis: an overview. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:786-789 [Conf]
  7. Shiann-Ning Jean, Chih-Wei Jim Chang, Sun-Yuan Kung
    Graceful Degradation Schemes for Static/Dynamic Wavefront Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:249-255 [Conf]
  8. Sun-Yuan Kung, Chih-Wei Jim Chang, Chein-Wei Jen
    Real-Time Configuration for Fault-Tolerant VLSI Array Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1986, pp:46-54 [Conf]
  9. Sun-Yuan Kung, Shiann-Ning Jean, Chih-Wei Jim Chang
    Fault-Tolerant Array Processors Using Single-Track Switches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1989, v:38, n:4, pp:501-514 [Journal]
  10. Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
    Fast postplacement optimization using functional symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:102-118 [Journal]
  11. Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska
    A new reasoning scheme for efficient redundancy addition and removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:945-951 [Journal]

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