The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Mango Chia-Tso Chao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wen-Long Wei
    Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1083-1088 [Conf]
  2. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng
    Coverage loss by using space compactors in presence of unknown values. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1053-1054 [Conf]
  3. Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
    Pattern Selection for Testing of Deep Sub-Micron Timing Defects. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:160- [Conf]
  4. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
    Response shaper: a novel technique to enhance unknown tolerance for output response compaction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:80-87 [Conf]
  5. Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang
    A clustering- and probability-based approach for time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:364-369 [Conf]
  6. Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
    ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:147-152 [Conf]
  7. Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang
    Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:335-347 [Conf]
  8. Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang
    A clustering- and probability-based approach for time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:2, pp:245-265 [Journal]

  9. Fault models for embedded-DRAM macros. [Citation Graph (, )][DBLP]


  10. A hybrid scheme for compacting test responses with unknown values. [Citation Graph (, )][DBLP]


  11. A metal-only-ECO solver for input-slew and output-loading violations. [Citation Graph (, )][DBLP]


  12. Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002