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Kamal Chaudhary: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kamal Chaudhary, Massoud Pedram
    A Near Optimal Algorithm for Technology Mapping Minimizing Area under Delay Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:492-498 [Conf]
  2. Sasan Iman, Massoud Pedram, Kamal Chaudhary
    Technology Mapping Using Fuzzy Logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:333-338 [Conf]
  3. Sudip Nag, Kamal Chaudhary
    Post-Placement Residual-Overlap Removal with Minimal Movement. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:581-586 [Conf]
  4. Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng
    Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:168-178 [Conf]
  5. Kamal Chaudhary, Akira Onozawa, Ernest S. Kuh
    A spacing algorithm for performance enhancement and cross-talk reduction. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:697-702 [Conf]
  6. Arvind Srinivasan, Kamal Chaudhary, Ernest S. Kuh
    RITUAL: Performance Driven Placement Algorithm for Small Cell ICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:48-51 [Conf]
  7. Massoud Pedram, Kamal Chaudhary, Ernest S. Kuh
    I/O Pad Assignment Based on the Circuit Structure. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:314-318 [Conf]
  8. Kamal Chaudhary, Massoud Pedram
    Computing the area versus delay trade-off curves in technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1480-1489 [Journal]
  9. Kamal Chaudhary, Peter Robinson
    Channel routing by sorting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:754-760 [Journal]
  10. Akira Onozawa, Kamal Chaudhary, Ernest S. Kuh
    Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:707-719 [Journal]

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