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Chien-In Henry Chen :
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Chien-In Henry Chen Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit. [Citation Graph (0, 0)][DBLP ] DAC, 1991, pp:287-290 [Conf ] Chien-In Henry Chen BISTSYN - A Built-In Self-Test Synthesizer. [Citation Graph (0, 0)][DBLP ] ICCAD, 1991, pp:240-243 [Conf ] Chien-In Henry Chen , Joel T. Yuen Logic partitioning to pseudo-exhaustive test for BIST design. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:646-649 [Conf ] Chien-In Henry Chen Allocation of Multiport Memory with Ports of Different Type in Register Transfer Level Synthesis. [Citation Graph (0, 0)][DBLP ] ICCD, 1991, pp:418-421 [Conf ] Chien-In Henry Chen , Joel T. Yuen Concurrent Test Scheduling in Built-In Self-Test Environment. [Citation Graph (0, 0)][DBLP ] ICCD, 1992, pp:256-259 [Conf ] Chien-In Henry Chen , Joel T. Yuen , Ji-Der Lee Autonomous-Tol for Hardware Partitioning in a Built-in Self-Test Environment. [Citation Graph (0, 0)][DBLP ] ICCD, 1992, pp:264-267 [Conf ] Chien-In Henry Chen , Kiran George Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2003, pp:521-524 [Conf ] Shailesh Radhakrishnan , Mingzhen Wang , Chien-In Henry Chen A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 2005, pp:6142-6145 [Conf ] Meghanad D. Wagh , Chien-In Henry Chen High-level design synthesis with redundancy removal for high speed testable adders. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 1999, pp:358-361 [Conf ] Chien-In Henry Chen , Kiran George Automated Synthesis of Configurable Two-dimensional Linear Feedback Shifter Registers for Random/Embedded Test Patterns. [Citation Graph (0, 0)][DBLP ] ISQED, 2003, pp:111-0 [Conf ] Kumar Yelamarthi , Chien-In Henry Chen Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization. [Citation Graph (0, 0)][DBLP ] ISQED, 2007, pp:426-431 [Conf ] Chien-In Henry Chen Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faults. [Citation Graph (0, 0)][DBLP ] ISSS, 2001, pp:203-208 [Conf ] Chien-In Henry Chen , Anup Kumar Comments on "Area-Time Optimal Adder Design". [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1994, v:43, n:4, pp:507-512 [Journal ] Chien-In Henry Chen , Joel T. Yuen Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1994, v:2, n:3, pp:273-291 [Journal ] Real-time FPGA-based implementation of digital instantaneous frequency measurement receiver. [Citation Graph (, )][DBLP ] Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic. [Citation Graph (, )][DBLP ] FPGA-Based 1.2 GHz Bandwidth Digital Instantaneous Frequency Measurement Receiver. [Citation Graph (, )][DBLP ] Search in 0.005secs, Finished in 0.006secs