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Publications of Author

1. Chung-Ping Chen, Yao-Wen Chang, D. F. Wong
   Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:405-408 [Conf]
   
2. Chung-Ping Chen, Yao-Ping Chen, D. F. Wong
   Optimal Wire-Sizing Formular Under the Elmore Delay Model. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:487-490 [Conf]
   
3. Chung-Ping Chen, Noel Menezes
   Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:502-506 [Conf]
   
4. Chung-Ping Chen, D. F. Wong
   Optimal Wire-Sizing Function with Fringing Capacitance Consideration. [Citation Graph (0, 0)][DBLP]
   DAC, 1997, pp:604-607 [Conf]
   
5. Chung-Ping Chen, D. F. Wong
   Error Bounded Padé Approximation via Bilinear Conformal Transformation. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:7-12 [Conf]
   
6. Vikas Sharma, Chien-Liang Chen, Chung-Ping Chen
   1-V 7-mW dual-band fast-locked frequency synthesizer. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:431-435 [Conf]
   
7. Chung-Ping Chen, Chris C. N. Chu, D. F. Wong
   Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:617-624 [Conf]
   
8. Chung-Ping Chen, Hai Zhou, D. F. Wong
   Optimal non-uniform wire-sizing under the Elmore delay model. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1996, pp:38-43 [Conf]
   
9. Noel Menezes, Chung-Ping Chen
   Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:476-0 [Conf]
   
10. Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong
    Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:1014-1025 [Journal]
    
11. 
    Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis. [Citation Graph (, )][DBLP]
    
    
12. 
    Interconnect delay and slew metrics using the beta distribution. [Citation Graph (, )][DBLP]
    
    
13. 
    Interconnect delay and slew metrics using the extreme value distribution. [Citation Graph (, )][DBLP]
    
    
14. 
    Performance measurement and queueing analysis of medium-high blocking probability of two and three parallel connection servers. [Citation Graph (, )][DBLP]