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Publications of Author

1. Chih-Ang Chen, Sandeep K. Gupta
   A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:209-214 [Conf]
   
2. Chih-Ang Chen, Sandeep K. Gupta
   BIST Test Pattern Generators for Stuck-Open and Delay Testing. [Citation Graph (0, 0)][DBLP]
   EDAC-ETC-EUROASIC, 1994, pp:289-296 [Conf]
   
3. Chi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain
   Low power state assignment targeting two-and multi-level logic implementations. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1994, pp:82-87 [Conf]
   
4. Chih-Ang Chen, Sandeep K. Gupta
   A Methodology to Design Efficient BIST Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
   ITC, 1995, pp:814-823 [Conf]
   
5. Chih-Ang Chen, Sandeep K. Gupta
   BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1996, v:45, n:3, pp:257-269 [Journal]
   
6. Chih-Ang Chen, Sandeep K. Gupta
   Design of efficient BIST test pattern generators for delay testing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1568-1575 [Journal]
   
7. Chih-Ang Chen, Sandeep K. Gupta
   Efficient BIST TPG design and test set compaction via input reduction. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:692-705 [Journal]