The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Chau-Shen Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Low Power FPGA Design - A Re-engineering Approach. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:656-661 [Conf]
  2. Chau-Shen Chen, Kuang-Hui Lin, TingTing Hwang
    Layout Driven Selecting and Chaining of Partial Scan. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:262-267 [Conf]
  3. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Architecture driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:408-411 [Conf]
  4. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-optimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:123-127 [Conf]
  5. Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin
    Combining technology mapping and placement for delay-minimization in FPGA designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1076-1084 [Journal]
  6. Chau-Shen Chen, TingTing Hwang, C. L. Liu
    Architecture driven circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:2, pp:383-389 [Journal]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002