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Publications of Author

1. Xiangfeng Chen, Peichen Pan, C. L. Liu
   Desensitization for Power Reduction in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:795-800 [Conf]
   
2. Peichen Pan
   Performance-Driven Integration of Retiming and Resynthesis. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:243-246 [Conf]
   
3. Peichen Pan, Sai-keung Dong, C. L. Liu
   Optimal Graph Constraint Reduction for Symbolic Layout Compaction. [Citation Graph (0, 0)][DBLP]
   DAC, 1993, pp:401-406 [Conf]
   
4. Peichen Pan, C. L. Liu
   Partial Scan with Pre-selected Scan Signals. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:189-194 [Conf]
   
5. Peichen Pan, C. L. Liu
   Optimal Clock Period FPGA Technology Mapping for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:720-725 [Conf]
   
6. Peichen Pan, C. L. Liu
   Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance. [Citation Graph (0, 0)][DBLP]
   FPGA, 1996, pp:58-64 [Conf]
   
7. Peichen Pan, Chih-Chang Lin
   A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 1998, pp:35-42 [Conf]
   
8. Peichen Pan, C. L. Liu
   Area minimization for general floorplans. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1992, pp:606-609 [Conf]
   
9. Peichen Pan, Weiping Shi, C. L. Liu
   Area minimization for hierarchical floorplans. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1994, pp:436-440 [Conf]
   
10. Arvind K. Karandikar, Peichen Pan, C. L. Liu
    Optimal Clock Period Clustering for Sequential Circuits with Retiming. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:122-127 [Conf]
    
11. Peichen Pan
    Continuous Retiming: Algorithms and Applications. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:116-121 [Conf]
    
12. Unni Narayanan, Peichen Pan, C. L. Liu
    Low power logic synthesis under a general delay model. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:209-214 [Conf]
    
13. Peichen Pan, Guohua Chen
    Optimal Retiming for Initial State Computation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:366-371 [Conf]
    
14. Prashant Saxena, Peichen Pan, C. L. Liu
    The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:402-407 [Conf]
    
15. Peichen Pan, Sai-keung Dong, C. L. Liu
    Optimal Graph Constraint Reduction for Symbolic Layout Compaction. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1997, v:18, n:4, pp:560-574 [Journal]
    
16. Peichen Pan, Weiping Shi, C. L. Liu
    Area Minimization for Hierarchical Floorplans. [Citation Graph (0, 0)][DBLP]
    Algorithmica, 1996, v:15, n:6, pp:550-571 [Journal]
    
17. Peichen Pan, C. L. Liu
    Partial Scan with Preselected Scan Signals. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:9, pp:1000-1005 [Journal]
    
18. Peichen Pan, Arvind K. Karandikar, C. L. Liu
    Optimal clock period clustering for sequential circuits with retiming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:6, pp:489-498 [Journal]
    
19. Peichen Pan, C. L. Liu
    Area minimization for floorplans. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:123-132 [Journal]
    
20. Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya
    Monotone bipartitioning problem in a planar point set with applications to VLSI. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:2, pp:231-248 [Journal]
    
21. Peichen Pan, C. L. Liu
    Optimal clock period FPGA technology mapping for sequential circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:437-462 [Journal]