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Zhanping Chen:
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- Zhanping Chen, Kaushik Roy
A Power Macromodeling Technique Based on Power Sensitivity. [Citation Graph (0, 0)][DBLP] DAC, 1998, pp:678-683 [Conf]
- Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. [Citation Graph (0, 0)][DBLP] DAC, 1998, pp:489-494 [Conf]
- Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. [Citation Graph (0, 0)][DBLP] DAC, 1999, pp:430-435 [Conf]
- Zhanping Chen, Kaushik Roy, Tan-Li Chou
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. [Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:40-44 [Conf]
- Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
Estimation of power sensitivity in sequential circuits with power macromodeling application. [Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:468-472 [Conf]
- Kaushik Roy, Liqiong Wei, Zhanping Chen
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. [Citation Graph (0, 0)][DBLP] ISCAS (1), 1999, pp:366-370 [Conf]
- Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. [Citation Graph (0, 0)][DBLP] ISLPED, 1998, pp:239-244 [Conf]
- James Tschanz, Siva Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. [Citation Graph (0, 0)][DBLP] ISLPED, 2001, pp:147-152 [Conf]
- Zhanping Chen, Liqiong Wei, Kaushik Roy
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. [Citation Graph (0, 0)][DBLP] ISQED, 2000, pp:181-188 [Conf]
- Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2002, v:19, n:2, pp:24-33 [Journal]
- Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
Estimation of power dissipation using a novel power macromodelingtechnique. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:11, pp:1363-1369 [Journal]
- Zhanping Chen, Kaushik Roy, Tan-Li Chou
Efficient statistical approach to estimate power considering uncertain properties of primary inputs. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:484-492 [Journal]
- Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
Design and optimization of dual-threshold circuits for low-voltage low-power applications. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:16-24 [Journal]
- Zhanping Chen, Liqiong Wei, Kaushik Roy
On effective IDDQ testing of low-voltage CMOS circuits using leakage control techniques. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:718-725 [Journal]
- Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes
Vertically integrated SOI circuits for low-power and high-performance applications. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:351-362 [Journal]
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