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Abhijit Dharchoudhury: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang
    iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:548-551 [Conf]
  2. Abhijit Dharchoudhury, Sung-Mo Kang
    An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:704-709 [Conf]
  3. Abhijit Dharchoudhury, Sung-Mo Kang
    Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:154-158 [Conf]
  4. Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden
    Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:738-743 [Conf]
  5. Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw
    Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:388-391 [Conf]
  6. Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw
    Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:436-441 [Conf]
  7. Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija
    CMOS Combinational Circuit Sizing by Stage-wise Tapering. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:985-988 [Conf]
  8. Abhijit Dharchoudhury, Sung-Mo Kang, H. Cha, J. H. Patel
    Fast timing simulation of transient faults in digital circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:719-722 [Conf]
  9. Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee
    Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:190-194 [Conf]
  10. Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, G. Vijayan, David Blaauw
    Library-less synthesis for static CMOS combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:658-662 [Conf]
  11. Abhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning
    Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:143-148 [Conf]
  12. David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
    Emerging power management tools for processor design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:143-148 [Conf]
  13. Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury
    A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:175-180 [Conf]
  14. Abhijit Dharchoudhury, Sung-Mo Kang
    Worst-case analysis and optimization of VLSI circuit performances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:481-492 [Journal]

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