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Tracy Larrabee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Brian Chess, Tracy Larrabee
    Bridge Fault simulation strategies for CMOS integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:458-462 [Conf]
  2. Haluk Konuk, F. Joel Ferguson, Tracy Larrabee
    Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:345-351 [Conf]
  3. Brian Chess, Tracy Larrabee
    Generating Test Patterns for Bridge Faults in CMOS ICs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:165-170 [Conf]
  4. Mark J. Boyd, Tracy Larrabee
    A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:13-21 [Conf]
  5. Brian Chess, David B. Lavo, F. Joel Ferguson, Tracy Larrabee
    Diagnosis of realistic bridging faults with single stuck-at information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:185-192 [Conf]
  6. Brian Chess, Anthony Freitas, F. Joel Ferguson, Tracy Larrabee
    Testing CMOS Logic Gates for Realistic Shorts. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:395-402 [Conf]
  7. F. Joel Ferguson, Tracy Larrabee
    Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:492-499 [Conf]
  8. Tracy Larrabee
    Efficient Generation of Test Patterns Using Boolean Difference. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:795-802 [Conf]
  9. David B. Lavo, Brian Chess, Tracy Larrabee, Ismed Hartanto
    Probabilistic mixed-model fault diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:1084-1093 [Conf]
  10. David B. Lavo, Ismed Hartanto, Tracy Larrabee
    Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:250-259 [Conf]
  11. David B. Lavo, Tracy Larrabee
    Making cause-effect cost effective: low-resolution fault dictionaries. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:278-286 [Conf]
  12. David B. Lavo, Tracy Larrabee, Brian Chess
    Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:611-619 [Conf]
  13. David B. Lavo, Tracy Larrabee, Jonathon E. Colburn
    Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1065-1072 [Conf]
  14. David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler
    Bridging Fault Diagnosis in the Absence of Physical Information. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:887-893 [Conf]
  15. Jayashree Saxena, Kenneth M. Butler, Hari Balachandran, David B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess
    On applying non-classical defect models to automated diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:748-757 [Conf]
  16. Tracy Larrabee, Jon Colbum
    Yield Optimization and Its Relation to Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:281-282 [Conf]
  17. Douglas Williams, F. Joel Ferguson, Tracy Larrabee
    A Study on the Utility of Using Expected Quality Level as a Design for Testability Metric. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:274-282 [Conf]
  18. Brian Chess, Tracy Larrabee
    Logic Testing of Bridging Faults in CMOS Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:3, pp:338-345 [Journal]
  19. Brian Chess, Tracy Larrabee
    Creating small fault dictionaries [logic circuit fault diagnosis]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:346-356 [Journal]
  20. Haluk Konuk, F. Joel Ferguson, Tracy Larrabee
    Charge-based fault simulation for CMOS network breaks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1555-1567 [Journal]
  21. Tracy Larrabee
    Test pattern generation using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:4-15 [Journal]
  22. David B. Lavo, Brian Chess, Tracy Larrabee, F. Joel Ferguson
    Diagnosing realistic bridging faults with single stuck-at information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:255-268 [Journal]

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