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Publications of Author

1. Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
   Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2. [Citation Graph (0, 0)][DBLP]
   DAC, 1988, pp:471-475 [Conf]
   
2. Surendra Nahar, Sartaj Sahni
   A time and space efficient net extractor. [Citation Graph (0, 0)][DBLP]
   DAC, 1986, pp:411-417 [Conf]
   
3. Surendra Nahar, Sartaj Sahni, Eugene Shragowitz
   Simulated annealing and combinatorial optimization. [Citation Graph (0, 0)][DBLP]
   DAC, 1986, pp:293-299 [Conf]
   
4. So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
   Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. [Citation Graph (0, 0)][DBLP]
   DAC, 1993, pp:395-400 [Conf]
   
5. Surendra Nahar, Sartaj Sahni, Eugene Shragowitz
   Experiments with simulated annealing. [Citation Graph (0, 0)][DBLP]
   DAC, 1985, pp:748-752 [Conf]
   
6. Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo
   Time-efficient VLSI artwork analysis algorithms in GOALIE2. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:640-648 [Journal]
   
7. Surendra Nahar, Sartaj K. Sahni
   Fast algorithm for polygon decomposition. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:473-483 [Journal]
   
8. So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo
   A cell-based hierarchical pitchmatching compaction using minimal LP. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:523-526 [Journal]