Search the dblp DataBase

Publications of Author

1. Goodwin R. Chin, Walter C. Dietrich Jr., Duane S. Boning, Alexander S. Wong, Andrew R. Neureuther, Robert W. Dutton
   Linking TCAD to EDA - Benefits and Issues. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:573-578 [Conf]
   
2. Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha Chandrakasan, Rakesh Vallishayee, Sani R. Nassif
   A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:172-175 [Conf]
   
3. James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning
   Interval-valued statistical modeling of oxide chemical-mechanical polishing. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:141-148 [Conf]
   
4. Sani R. Nassif, Duane S. Boning, Nagib Hakim
   The care and feeding of your statistical static timer. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2004, pp:138-139 [Conf]
   
5. Duane S. Boning
   Test Structures for Circuit Yield Assessment and Modeling. [Citation Graph (0, 0)][DBLP]
   ISQED, 2003, pp:8- [Conf]
   
6. Duane S. Boning, Karthik Balakrishnan, Hong Cai, Nigel Drego, Ali Farahanchi, Karen Gettings, Daihyun Lim, Ajay Somani, Hayden Taylor, Daniel Truque, Xiaolin Xie
   Variation. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:15-20 [Conf]
   
7. Nigel Drego, Anantha Chandrakasan, Duane S. Boning
   A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays. [Citation Graph (0, 0)][DBLP]
   ISQED, 2007, pp:281-286 [Conf]
   
8. Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu
   Test structures for delay variability. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:109- [Conf]
   
9. K. S. V. Gopalarao, Uttiya Dasgupta, Rajeev Jain, Duane S. Boning, Purnendu K. Mozumder, V. Chandramouli
   An Integrated Technology CAD System for Process and Device Designers. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1993, pp:287-292 [Conf]
   
10. Taber H. Smith, Aaron E. Gower, Duane S. Boning
    A Matrix Math Library for Java. [Citation Graph (0, 0)][DBLP]
    Concurrency - Practice and Experience, 1997, v:9, n:11, pp:1127-1137 [Journal]
    
11. Duane S. Boning, Michael L. Heytens, Alexander S. Wong
    The intertool profile interchange format: an object-oriented approach [semiconductor technology CAD/CAM]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:9, pp:1150-1156 [Journal]
    
12. Martin D. Giles, Duane S. Boning, Goodwin R. Chin, Walter C. Dietrich Jr., Michael S. Karasick, Mark E. Law, Purnendu K. Mozumder, Lee R. Nackman, V. T. Rajan, Duncan M. Hank Walker, Robert H. Wang, Alexander S. Wong
    Semiconductor wafer representation for TCAD. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:82-95 [Journal]
    
13. K. S. V. Gopalarao, Purnendu K. Mozumder, Duane S. Boning
    An integrated technology CAD system for process and device designers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:482-490 [Journal]