Search the dblp DataBase

Publications of Author

1. Ching-Te Chuang, Ruchir Puri
   SOI Digital CMOS VLSI - a Design Perspective. [Citation Graph (0, 0)][DBLP]
   DAC, 1999, pp:709-714 [Conf]
   
2. Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang
   SOI for asynchronous dynamic circuits. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2001, pp:37-42 [Conf]
   
3. Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri
   Design and CAD Challenges in sub-90nm CMOS Technologies. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:129-137 [Conf]
   
4. Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
   New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:168-171 [Conf]
   
5. Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang
   "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). [Citation Graph (0, 0)][DBLP]
   ISLPED, 2000, pp:203-206 [Conf]
   
6. Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang
   Nanoscale CMOS circuit leakage power reduction by double-gate device. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2004, pp:102-107 [Conf]
   
7. Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang
   Strained-si devices and circuits for low-power applications. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2003, pp:180-183 [Conf]
   
8. Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy
   Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2005, pp:8-13 [Conf]
   
9. Ruchir Puri, Ching-Te Chuang
   Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1999, pp:223-228 [Conf]
   
10. Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim
    Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:153-158 [Conf]
    
11. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
    Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:410-415 [Conf]
    
12. Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong
    Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:145-152 [Conf]
    
13. Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang
    High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:758-761 [Conf]
    
14. Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang
    A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:44-49 [Conf]
    
15. Rajiv V. Joshi, K. Kroell, Ching-Te Chuang
    A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:832-0 [Conf]
    
16. Rajiv V. Joshi, S. S. Kang, N. Zamdmar, A. Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez
    Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:697-702 [Conf]
    
17. Ruchir Puri, Ching-Te Chuang
    SOI Digital Circuits: Design Issues. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:474-479 [Conf]
    
18. Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang
    A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:665-672 [Conf]
    
19. Rajiv V. Joshi, Ching-Te Chuang, S. K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi
    PD/SOI SRAM performance in presence of gate-to-body tunneling current. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1106-1113 [Journal]
    
20. 
    Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]
    
    
21. 
    Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. [Citation Graph (, )][DBLP]
    
    
22. 
    Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. [Citation Graph (, )][DBLP]
    
    
23. 
    A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. [Citation Graph (, )][DBLP]
    
    
24. 
    Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. [Citation Graph (, )][DBLP]
    
    
25. 
    Design and analysis of ultra-thin-body SOI based subthreshold SRAM. [Citation Graph (, )][DBLP]
    
    
26. 
    Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. [Citation Graph (, )][DBLP]
    
    
27. 
    On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. [Citation Graph (, )][DBLP]
    
    
28. 
    Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. [Citation Graph (, )][DBLP]
    
    
29. 
    On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. [Citation Graph (, )][DBLP]
    
    
30. 
    Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. [Citation Graph (, )][DBLP]