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Maciej J. Ciesielski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio
    A Unified Approach to Input-Output Encoding for FSM State Assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:176-181 [Conf]
  2. Donald A. Joy, Maciej J. Ciesielski
    Placement for Clock Period Minimization With Multiple Wave Propagation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:640-643 [Conf]
  3. Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski
    A new state assignment technique for testing and low power. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:510-513 [Conf]
  4. Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal
    BDS: a BDD-based logic optimization system. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:92-97 [Conf]
  5. Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre
    Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:285-291 [Conf]
  6. Jérémie Guillot, Emmanuel Boutillon, Q. Ren, Maciej J. Ciesielski, D. Gomez-Prado, Serkan Askar
    Efficient factorization of DSP transforms using taylor expansion diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:754-755 [Conf]
  7. Priyank Kalla, Maciej J. Ciesielski
    Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:638-642 [Conf]
  8. Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang
    A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:232-236 [Conf]
  9. Congguang Yang, Maciej J. Ciesielski
    Synthesis for Mixed CMOS/PTl Logic. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:750- [Conf]
  10. Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski
    LPSAT: a unified approach to RTL satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:398-402 [Conf]
  11. Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski
    Fast Computation of Data Correlation Using BDDs. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10122-10129 [Conf]
  12. Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
    An ILP Formulation for Yield-driven Architectural Synthesis. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:12-20 [Conf]
  13. Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
    Yield-aware Floorplanning. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:247-253 [Conf]
  14. Serkan Askar, Maciej J. Ciesielski
    Analytical approach to custom datapath design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:98-101 [Conf]
  15. Balakrishnan Iyer, Maciej J. Ciesielski
    Metamorphosis: state assignment by retiming and re-encoding. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:614-617 [Conf]
  16. Balakrishnan Iyer, Maciej J. Ciesielski
    Reencoding for cycle-time minimization under fixed encoding length. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:312-315 [Conf]
  17. Maya K. Yajnik, Maciej J. Ciesielski
    Finite State Machine Decomposition Using Multiway Partitioning. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:320-323 [Conf]
  18. Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal
    BDD Decomposition for Efficient Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:626-0 [Conf]
  19. Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
    Functional Test Generation using Constraint Logic Programming. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:375-387 [Conf]
  20. Wayne Burleson, L. W. Cotten, Fabian Klass, Maciej J. Ciesielski
    Forum: Wave-pipelining: Is it Practical? [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:163-166 [Conf]
  21. Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski
    Algorithms for Taylor Expansion Diagrams. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2004, pp:235-240 [Conf]
  22. Durgam Vahia, Maciej J. Ciesielski
    Transistor level placement for full custom datapath cell design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:158-163 [Conf]
  23. Priyank Kalla, Maciej J. Ciesielski
    A comprehensive approach to the partial scan problem using implicit state enumeration. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:651-657 [Conf]
  24. Imrich Chlamtac, Maciej J. Ciesielski, Andrea Fumagalli, Chester A. Ruszczyk, Gosse Wedzinga
    Intelligent Simulation for Computer Aided Design of Optical Networks. [Citation Graph (0, 0)][DBLP]
    ONDM, 1997, pp:73-86 [Conf]
  25. Priyank Kalla, Maciej J. Ciesielski
    Testability of Sequential Circuits with Multi-Cycle False Path. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:322-328 [Conf]
  26. Zafar Hasan, David Harrison, Maciej J. Ciesielski
    A Fast Partitioning Method for PLA-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:4, pp:34-39 [Journal]
  27. Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski
    Functional test generation based on word-level SAT. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2005, v:51, n:8, pp:488-511 [Journal]
  28. Maciej J. Ciesielski, Priyank Kalla, Serkan Askar
    Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:9, pp:1188-1201 [Journal]
  29. Maciej J. Ciesielski
    Two-Dimensional Routing for the Silc Silicon Compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:198-203 [Journal]
  30. Maciej J. Ciesielski
    Layer assignment for VLSI interconnect delay minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:6, pp:702-707 [Journal]
  31. Maciej J. Ciesielski, Serkan Askar, Samuel Levitin
    Analytical approach to layout generation of datapath cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1480-1488 [Journal]
  32. Maciej J. Ciesielski, E. Kinnen
    Digraph Relaxation for 2-Dimensional Placement of IC Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:55-66 [Journal]
  33. Maciej J. Ciesielski, Seiyang Yang
    PLADE: a two-stage PLA decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:943-954 [Journal]
  34. Donald A. Joy, Maciej J. Ciesielski
    Clock period minimization with wave pipelining. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:4, pp:461-472 [Journal]
  35. Priyank Kalla, Maciej J. Ciesielski
    A comprehensive approach to the partial scan problem using implicitstate enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:810-826 [Journal]
  36. Congguang Yang, Maciej J. Ciesielski
    BDS: a BDD-based logic optimization system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:7, pp:866-876 [Journal]
  37. Seiyang Yang, Maciej J. Ciesielski
    Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:1, pp:4-12 [Journal]
  38. Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski
    Retiming-based factorization for sequential logic optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:373-398 [Journal]
  39. Maciej J. Ciesielski, Serkan Askar, D. Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon
    Data-flow transformations using Taylor expansion diagrams. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:455-460 [Conf]
  40. Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu
    Wave-pipelining: a tutorial and research survey. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:464-474 [Journal]

  41. A fast two-pass HDL simulation with on-demand dump. [Citation Graph (, )][DBLP]


  42. Optimizing data flow graphs to minimize hardware implementation. [Citation Graph (, )][DBLP]


  43. Simulation Acceleration with HW Re-Compilation Avoidance. [Citation Graph (, )][DBLP]


  44. High-Level Dataflow Transformations Using Taylor Expansion Diagrams. [Citation Graph (, )][DBLP]


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