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Balaram Sinharoy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam Chu, Donald Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, Steve Dodson
Design and implementation of the POWER5 microprocessor. [Citation Graph (0, 0)][DBLP]
DAC, 2004, pp:670-672 [Conf] - Balaram Sinharoy, Rama Govindaraju
Improving Software MP Efficiency for Shared Memory Systems. [Citation Graph (0, 0)][DBLP]
HICSS (1), 1996, pp:111-120 [Conf] - Hans M. Jacobson, Pradip Bose, Zhigang Hu, Alper Buyuktosunoglu, Victor V. Zyuban, Rick Eickemeyer, Lee Eisen, John Griswell, Doug Logan, Balaram Sinharoy, Joel M. Tendler
Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. [Citation Graph (0, 0)][DBLP]
HPCA, 2005, pp:238-242 [Conf] - Wael El-Essawy, David H. Albonesi, Balaram Sinharoy
A microarchitectural-level step-power analysis tool. [Citation Graph (0, 0)][DBLP]
ISLPED, 2002, pp:263-266 [Conf] - William Maniatty, Boleslaw K. Szymanski, Balaram Sinharoy
Efficiency of Data Alignment on Maspar. [Citation Graph (0, 0)][DBLP]
SIGPLAN Workshop, 1992, pp:48-51 [Conf] - Balaram Sinharoy
Optimized Thread Creation for Processor Multithreading. [Citation Graph (0, 0)][DBLP]
Comput. J., 1997, v:40, n:6, pp:388-400 [Journal] - Balaram Sinharoy, Ronald N. Kalla, Joel M. Tendler, Richard J. Eickemeyer, Jody B. Joyner
POWER5 system microarchitecture. [Citation Graph (0, 0)][DBLP]
IBM Journal of Research and Development, 2005, v:49, n:4-5, pp:505-522 [Journal] - Joel M. Tendler, J. Steve Dodson, J. S. Fields Jr., Hung Le, Balaram Sinharoy
POWER4 system microarchitecture. [Citation Graph (0, 0)][DBLP]
IBM Journal of Research and Development, 2002, v:46, n:1, pp:5-26 [Journal] - Boleslaw K. Szymanski, Balaram Sinharoy
Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix. [Citation Graph (0, 0)][DBLP]
Inf. Process. Lett., 1992, v:42, n:3, pp:121-126 [Journal] - Boleslaw K. Szymanski, Balaram Sinharoy
Corrigenda: Complexity of the Closest Vector Problem in a Lattice Generated by (0, 1)-Matrix. [Citation Graph (0, 0)][DBLP]
Inf. Process. Lett., 1992, v:43, n:3, pp:167- [Journal] - Balaram Sinharoy, Boleslaw K. Szymanski
Data and Task Alignment in Distributed Memory Architectures. [Citation Graph (0, 0)][DBLP]
J. Parallel Distrib. Comput., 1994, v:21, n:1, pp:61-74 [Journal] - Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler
IBM Power5 Chip: A Dual-Core Multithreaded Processor. [Citation Graph (0, 0)][DBLP]
IEEE Micro, 2004, v:24, n:2, pp:40-47 [Journal] - Boleslaw K. Szymanski, William Maniatty, Balaram Sinharoy
Simultaneous Parallel Reduction on SIMD Machines. [Citation Graph (0, 0)][DBLP]
Parallel Processing Letters, 1995, v:5, n:, pp:437-449 [Journal] - Balaram Sinharoy
Compiler optimization to improve data locality for processor multithreading. [Citation Graph (0, 0)][DBLP]
Scientific Programming, 1999, v:7, n:1, pp:21-37 [Journal]
POWER7 multi-core processor design. [Citation Graph (, )][DBLP]
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