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## Search the dblp DataBase
Joel R. Phillips:
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## Publications of Author- Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
**Robust Rational Function Approximation Algorithm for Model Generation.**[Citation Graph (0, 0)][DBLP] DAC, 1999, pp:207-212 [Conf] - Luca Daniel, Joel R. Phillips
**Model order reduction for strictly passive and causal distributed systems.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:46-51 [Conf] - Dan Feng, Joel R. Phillips, Keith Nabors, Kenneth S. Kundert, Jacob White
**Efficient Computation of Quasi-Periodic Circuit Operating Conditions via a Mixed Frequency/Time Approach.**[Citation Graph (0, 0)][DBLP] DAC, 1999, pp:635-640 [Conf] - Joe Kanapka, Joel R. Phillips, Jacob White
**Fast methods for extraction and sparsification of substrate coupling.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:738-743 [Conf] - Joel R. Phillips
**Projection frameworks for model reduction of weakly nonlinear systems.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:184-189 [Conf] - Joel R. Phillips, Luca Daniel, Luis Miguel Silveira
**Guaranteed passive balancing transformations for model order reduction.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:52-57 [Conf] - Luis Miguel Silveira, Joel R. Phillips
**Exploiting input information in a model reduction algorithm for massively coupled parasitic networks.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:385-388 [Conf] - Baolin Yang, Joel R. Phillips
**A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulation.**[Citation Graph (0, 0)][DBLP] DAC, 2000, pp:178-183 [Conf] - Baolin Yang, Joel R. Phillips
**Time-domain steady-state simulation of frequency-dependent components using multi-interval Chebyshev method.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:504-509 [Conf] - Carlos P. Coelho, Luis Miguel Silveira, Joel R. Phillips
**Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation.**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:923-930 [Conf] - Joel R. Phillips, Luis Miguel Silveira
**Poor Man's TBR: A Simple Model Reduction Scheme.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:938-943 [Conf] - Piet Wambacq, Gerd Vandersteen, Joel R. Phillips, Jaijeet S. Roychowdhury, Wolfgang Eberle, Baolin Yang, David E. Long, Alper Demir
**CAD for RF circuits.**[Citation Graph (0, 0)][DBLP] DATE, 2001, pp:520-529 [Conf] - Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
**A Convex Programming Approach to Positive Real Rational Approximation.**[Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:245-251 [Conf] - Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
**Optimization based passive constrained fitting.**[Citation Graph (0, 0)][DBLP] ICCAD, 2002, pp:775-780 [Conf] - Joel R. Phillips
**Variational interconnect analysis via PMTBR.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:872-879 [Conf] - Joel R. Phillips
**Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors.**[Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:96-102 [Conf] - Joel R. Phillips, João Afonso, Arlindo L. Oliveira, Luis Miguel Silveira
**Analog Macromodeling using Kernel Methods.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:446-453 [Conf] - Joel R. Phillips, Luis Miguel Silveira
**Simulation Approaches for Strongly Coupled Interconnect Systems.**[Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:430-0 [Conf] - Phillip Restle, Joel R. Phillips, Ibrahim M. Elfadel
**Interconnect in high speed designs: problems, methodologies and tools.**[Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:4- [Conf] - Edoardo Charbon, Joel R. Phillips
**Substrate Noise: Analysis, Models, and Optimization.**[Citation Graph (0, 0)][DBLP] VLSI, 1999, pp:456-472 [Conf] - Joel R. Phillips, Dan Feng
**Trends in RF Simulation Algorithms.**[Citation Graph (0, 0)][DBLP] VLSI, 1999, pp:557-568 [Conf] - Carlos P. Coelho, Joel R. Phillips, Luis Miguel Silveira
**A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:2, pp:293-301 [Journal] - Joel R. Phillips
**Projection-based approaches for model reduction of weakly nonlinear, time-varying systems.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:171-187 [Journal] - Joel R. Phillips, Luca Daniel, Luis Miguel Silveira
**Guaranteed passive balancing transformations for model order reduction.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1027-1041 [Journal] - Joel R. Phillips, Luis Miguel Silveira
**Poor man's TBR: a simple model reduction scheme.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:43-55 [Journal] - Joel R. Phillips, Jacob K. White
**A precorrected-FFT method for electrostatic analysis of complicated 3-D structures.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1059-1072 [Journal] - Saurabh K. Tiwary, Joel R. Phillips
**WAVSTAN: waveform based variational static timing analysis.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1000-1005 [Conf] - Luís Guerra e Silva, Luis Miguel Silveira, Joel R. Phillips
**Efficient computation of the worst-delay corner.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1617-1622 [Conf] - Zhenhai Zhu, Joel R. Phillips
**Random sampling of moment graph: a stochastic Krylov-reduction algorithm.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1502-1507 [Conf] - Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira
**Variation-Aware, Library Compatible Delay Modeling Strategy.**[Citation Graph (0, 0)][DBLP] VLSI-SoC, 2006, pp:122-127 [Conf] **Generalized Krylov recycling methods for solution of multiple related linear equation systems in electromagnetic analysis.**[Citation Graph (, )][DBLP]**Speedpath analysis under parametric timing models.**[Citation Graph (, )][DBLP]**Efficient Representation and Analysis of Power Grids.**[Citation Graph (, )][DBLP]**Extended Hamiltonian Pencil for passivity assessment and enforcement for S-parameter systems.**[Citation Graph (, )][DBLP]**First steps towards SAT-based formal analog verification.**[Citation Graph (, )][DBLP]**Sparse implicit projection (SIP) for reduction of general many-terminal networks.**[Citation Graph (, )][DBLP]**Fast and reliable passivity assessment and enforcement with extended Hamiltonian pencil.**[Citation Graph (, )][DBLP]
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