The SCEAS System
| |||||||

## Search the dblp DataBase
Yuzheng Ding:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Jason Cong, Yuzheng Ding
**On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping.**[Citation Graph (0, 0)][DBLP] DAC, 1993, pp:213-218 [Conf] - Jason Cong, Yuzheng Ding
**On Nominal Delay Minimization in LUT-based FPGA Technology Mapping.**[Citation Graph (0, 0)][DBLP] FPGA, 1995, pp:82-88 [Conf] - Jason Cong, John Peck, Yuzheng Ding
**RASP: A General Logic Synthesis System for SRAM-Based FPGAs.**[Citation Graph (0, 0)][DBLP] FPGA, 1996, pp:137-143 [Conf] - Jason Cong, Chang Wu, Yuzheng Ding
**Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.**[Citation Graph (0, 0)][DBLP] FPGA, 1999, pp:29-35 [Conf] - Yuzheng Ding, Peter Suaris, Nan-Chi Chou
**The effect of post-layout pin permutation on timing.**[Citation Graph (0, 0)][DBLP] FPGA, 2005, pp:41-50 [Conf] - Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou
**Incremental physical resynthesis for timing optimization.**[Citation Graph (0, 0)][DBLP] FPGA, 2004, pp:99-108 [Conf] - Jason Cong, Yuzheng Ding
**An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.**[Citation Graph (0, 0)][DBLP] ICCAD, 1992, pp:48-53 [Conf] - Jason Cong, Yuzheng Ding
**Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs.**[Citation Graph (0, 0)][DBLP] ICCAD, 1993, pp:110-114 [Conf] - Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen
**An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization.**[Citation Graph (0, 0)][DBLP] ICCD, 1992, pp:154-158 [Conf] - Yuzheng Ding, Mark Allen Weiss
**The K-D Heap: An Efficient Multi-dimensional Priority Queue.**[Citation Graph (0, 0)][DBLP] WADS, 1993, pp:302-313 [Conf] - Yuzheng Ding, Mark Allen Weiss
**The Relaxed min-max Heap.**[Citation Graph (0, 0)][DBLP] Acta Inf., 1993, v:30, n:3, pp:215-231 [Journal] - Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen
**LUT-based FPGA technology mapping under arbitrary net-delay models.**[Citation Graph (0, 0)][DBLP] Computers & Graphics, 1994, v:18, n:4, pp:507-516 [Journal] - Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar
**DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization.**[Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 1992, v:9, n:3, pp:7-20 [Journal] - Yuzheng Ding, Mark Allen Weiss
**On the Complexity of Building an Interval Heap.**[Citation Graph (0, 0)][DBLP] Inf. Process. Lett., 1994, v:50, n:3, pp:143-144 [Journal] - Jason Cong, Yuzheng Ding
**FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:1-12 [Journal] - Jason Cong, Yuzheng Ding
**Combinational logic synthesis for LUT based field programmable gate arrays.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:2, pp:145-204 [Journal] - Jason Cong, Yuzheng Ding
**On area/depth trade-off in LUT-based FPGA technology mapping.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:137-148 [Journal]
Search in 0.008secs, Finished in 0.009secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |