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Yean-Yow Hwang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jason Cong, Yean-Yow Hwang
    Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:726-729 [Conf]
  2. Jason Cong, Yean-Yow Hwang, Songjie Xu
    Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:373-378 [Conf]
  3. Jason Cong, Yean-Yow Hwang
    Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:68-74 [Conf]
  4. Jason Cong, Yean-Yow Hwang
    Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:35-42 [Conf]
  5. Jason Cong, Yean-Yow Hwang
    Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:27-34 [Conf]
  6. Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong
    Intellectual property protection by watermarking combinational logic synthesis solutions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:194-198 [Conf]
  7. Jason Cong, Yean-Yow Hwang
    Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1077-1090 [Journal]
  8. Jason Cong, Yean-Yow Hwang
    Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:2, pp:193-225 [Journal]

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